Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environ...Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.展开更多
Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in cu...Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.展开更多
An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fix...An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fixed initial radius, the ILSD adopts an adaptive radius to accelerate the list cdnstruction. Characterized by low-complexity and radius-insensitivity, the proposed algorithm makes iterative joint detection and decoding more realizable in multiple-antenna systems. Simulation results show that computational savings of ILSD over LSD are more apparent with more transmit antennas or larger constellations, and with no performance degradation. Because the complexity of the ILSD algorithm almost keeps invariant with the increasing of initial radius, the BER performance can be improved by selecting a sufficiently large radius.展开更多
This paper presented a concatenated maximum-likelihood (ML) decoder for space-time/space-frequency block coded orthogonal frequency diversion multiplexing (ST/SFBC-OFDM) systems in double selective fading channels. Th...This paper presented a concatenated maximum-likelihood (ML) decoder for space-time/space-frequency block coded orthogonal frequency diversion multiplexing (ST/SFBC-OFDM) systems in double selective fading channels. The proposed decoder first detects space-time or space-frequency codeword elements separately. Then, according to the coarsely estimated codeword elements, the ML decoding is performed in a smaller constellation element set to searching final codeword. It is proved that the proposed decoder has optimal performances if and only if subchannels are constant during a codeword interval. The simulation results show that the performances of proposed decoder is close to that of the optimal ML decoder in severe Doppler and delay spread channels. However, the complexity of proposed decoder is much lower than that of the optimal ML decoder.展开更多
Turbo code has been shown to have ability to achieve performance that is close to Shannon limit. It has been adopted by various commercial communication systems. Both universal mobile telecommunications system (UMTS) ...Turbo code has been shown to have ability to achieve performance that is close to Shannon limit. It has been adopted by various commercial communication systems. Both universal mobile telecommunications system (UMTS) TDD and FDD have also employed turbo code as the error correction coding scheme. It outperforms convolutional code in large block size, but because of its time delay, it is often only used in the non-real-time service. In this paper, we discuss the encoder and decoder structure of turbo code in B3G mobile communication System. In addition, various decoding techniques, such as the Log-MAP, Max-log-MAP and SOVA algorithm for non-real-time service are deduced and compared. The performance results of decoder and algorithms in different configurations are also shown.展开更多
The encoding/decoding scheme based on Fiber Bragg Grating (FBG) for Optical Code Division Multiple Access (OCDMA) system is analyzed and the whole process from transmitting end to receiving end is researched in detail...The encoding/decoding scheme based on Fiber Bragg Grating (FBG) for Optical Code Division Multiple Access (OCDMA) system is analyzed and the whole process from transmitting end to receiving end is researched in detail. The mathematical mode including signal transmission, summing, receiving and recovering are established respectively. One of the main sources of Bit Error Rate (BER) of OCDMA system based on FBGs is the unevenness of signal power spectrum, which leads to the chip powers unequal with each other. The Signal to Interfere Ratio (SIR) and BER performance of the system are studied and simulated at the case with uneven distribution of chips' powers.展开更多
This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Syste...This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.展开更多
In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete mem...In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete memoryless channels(BDMCs),the proposed decoders quantize the virtual subchannels of polar codes to maximize mutual information(MMI)between source bits and quantized symbols.The nested structure of polar codes ensures that the MMI quantization can be implemented stage by stage.Simulation results show that the proposed MMI decoders with 4 quantization bits outperform the existing nonuniform quantized decoders that minimize mean-squared error(MMSE)with 4 quantization bits,and yield even better performance than uniform MMI quantized decoders with 5 quantization bits.Furthermore,the proposed 5-bit quantized MMI decoders approach the floating-point decoders with negligible performance loss.展开更多
A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） mult...A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.展开更多
The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transisto...The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.展开更多
A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous compa...A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.展开更多
Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ra...Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ratio （SNR） compared to the coherent case. To overcome the gap, an effective differential encoding and decoding scheme for multiband UWB systems is proposed. The proposed scheme employs the parallel concatenation of two recursive differential unitary space-frequency encoders at the transmitter. At the receiver, two component decoders iteratively decode information bits by interchanging soft metric values between each other. To reduce the computation complexity, a decoding algorithm which only uses transition probability to calculate the log likelihood ratios （LLRs） for the decoded bits is given. Simulation results show that the proposed scheme can dramatically outperform the conventional differential and even coherent detection at high SNR with a few iterations.展开更多
Constituted by BCH component codes and its ordered statistics decoding(OSD),the successive cancellation list(SCL)decoding of U-UV structural codes can provide competent error-correction performance in the short-to-med...Constituted by BCH component codes and its ordered statistics decoding(OSD),the successive cancellation list(SCL)decoding of U-UV structural codes can provide competent error-correction performance in the short-to-medium length regime.However,this list decoding complexity becomes formidable as the decoding output list size increases.This is primarily incurred by the OSD.Addressing this challenge,this paper proposes the low complexity SCL decoding through reducing the complexity of component code decoding,and pruning the redundant SCL decoding paths.For the former,an efficient skipping rule is introduced for the OSD so that the higher order decoding can be skipped when they are not possible to provide a more likely codeword candidate.It is further extended to the OSD variant,the box-andmatch algorithm(BMA),in facilitating the component code decoding.Moreover,through estimating the correlation distance lower bounds(CDLBs)of the component code decoding outputs,a path pruning(PP)-SCL decoding is proposed to further facilitate the decoding of U-UV codes.In particular,its integration with the improved OSD and BMA is discussed.Simulation results show that significant complexity reduction can be achieved.Consequently,the U-UV codes can outperform the cyclic redundancy check(CRC)-polar codes with a similar decoding complexity.展开更多
A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not ...A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.展开更多
This paper studies the decoding performance of low-density parity-check(LDPC)codes in a serial concatenation system with polar codes employing the successive cancellation(SC)decoding.It is known that the absolute inco...This paper studies the decoding performance of low-density parity-check(LDPC)codes in a serial concatenation system with polar codes employing the successive cancellation(SC)decoding.It is known that the absolute incorrect log-likelihood ratio(LLR)values from the SC decoding can be very large.This phenomenon dramatically deteriorates the error correcting performance of the outer LDPC codes.In this paper,the LLR values of polar codes are regulated by a log processing before being sent to the LDPC decoder.Simulation results show that the log processing is an efficient approach with a low optimization complexity compared with the existing procedures to improve the performance of the serial concatenation systems.展开更多
Aiming at the optimum path excluding characteristics and the full constellation searching characteristics of the K-best detection algorithm, an improved-performance K-best detection algorithm and several reduced-compl...Aiming at the optimum path excluding characteristics and the full constellation searching characteristics of the K-best detection algorithm, an improved-performance K-best detection algorithm and several reduced-complexity K-best detection algorithms are proposed. The improved-performance K-best detection algorithm deploys minimum mean square error （MMSE） filtering of a channel matrix before QR decomposition. This algorithm can decrease the probability of excluding the optimum path and achieve better performance. The reducedcomplexity K-best detection algorithms utilize a sphere decoding method to reduce searching constellation points. Simulation results show that the improved performance K-best detection algorithm obtains a 1 dB performance gain compared to the K- best detection algorithm based on sorted QR decomposition （SQRD）. Performance loss occurs when K = 4 in reduced complexity K-best detection algorithms. When K = 8, the reduced complexity K-best detection algorithms require less computational effort compared with traditional K-best detection algorithms and achieve the same performance.展开更多
Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development...Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.展开更多
A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces...A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.展开更多
基金supported by the National Natural Science Foundation of China under Grant No.62001440。
文摘Quantum key distribution is increasingly transitioning toward network applications,necessitating advancements in system performance,including photonic integration for compact designs,enhanced stability against environmental disturbances,higher key rates,and improved efficiency.In this letter,we propose an orthogonal polarization exchange reflector Michelson interferometer model to address quantum channel disturbances caused by environmental factors.Based on this model,we designed a Sagnac reflector-Michelson interferometer decoder and verified its performance through an interference system.The interference fringe visibility exceeded 98%across all four coding phases at 625 MHz.These results indicate that the decoder effectively mitigates environmental interference while supporting high-speed modulation frequencies.In addition,the proposed anti-interference decoder,which does not rely on magneto-optical devices,is well-suited for photonic integration,aligning with the development trajectory for next-generation quantum communication devices.
基金Project supported by the Natural Science Foundation of Shandong Province,China(Grant No.ZR2021MF049)Joint Fund of Natural Science Foundation of Shandong Province(Grant Nos.ZR2022LLZ012 and ZR2021LLZ001)the Key R&D Program of Shandong Province,China(Grant No.2023CXGC010901)。
文摘Quantum computing has the potential to solve complex problems that are inefficiently handled by classical computation.However,the high sensitivity of qubits to environmental interference and the high error rates in current quantum devices exceed the error correction thresholds required for effective algorithm execution.Therefore,quantum error correction technology is crucial to achieving reliable quantum computing.In this work,we study a topological surface code with a two-dimensional lattice structure that protects quantum information by introducing redundancy across multiple qubits and using syndrome qubits to detect and correct errors.However,errors can occur not only in data qubits but also in syndrome qubits,and different types of errors may generate the same syndromes,complicating the decoding task and creating a need for more efficient decoding methods.To address this challenge,we used a transformer decoder based on an attention mechanism.By mapping the surface code lattice,the decoder performs a self-attention process on all input syndromes,thereby obtaining a global receptive field.The performance of the decoder was evaluated under a phenomenological error model.Numerical results demonstrate that the decoder achieved a decoding accuracy of 93.8%.Additionally,we obtained decoding thresholds of 5%and 6.05%at maximum code distances of 7 and 9,respectively.These results indicate that the decoder used demonstrates a certain capability in correcting noise errors in surface codes.
基金The National Natural Science Founda-tion of China ( No 60496316)the National Hi-Tech Re-search and Development Program (863) of China (No2006-AA01Z270)
文摘An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fixed initial radius, the ILSD adopts an adaptive radius to accelerate the list cdnstruction. Characterized by low-complexity and radius-insensitivity, the proposed algorithm makes iterative joint detection and decoding more realizable in multiple-antenna systems. Simulation results show that computational savings of ILSD over LSD are more apparent with more transmit antennas or larger constellations, and with no performance degradation. Because the complexity of the ILSD algorithm almost keeps invariant with the increasing of initial radius, the BER performance can be improved by selecting a sufficiently large radius.
文摘This paper presented a concatenated maximum-likelihood (ML) decoder for space-time/space-frequency block coded orthogonal frequency diversion multiplexing (ST/SFBC-OFDM) systems in double selective fading channels. The proposed decoder first detects space-time or space-frequency codeword elements separately. Then, according to the coarsely estimated codeword elements, the ML decoding is performed in a smaller constellation element set to searching final codeword. It is proved that the proposed decoder has optimal performances if and only if subchannels are constant during a codeword interval. The simulation results show that the performances of proposed decoder is close to that of the optimal ML decoder in severe Doppler and delay spread channels. However, the complexity of proposed decoder is much lower than that of the optimal ML decoder.
文摘Turbo code has been shown to have ability to achieve performance that is close to Shannon limit. It has been adopted by various commercial communication systems. Both universal mobile telecommunications system (UMTS) TDD and FDD have also employed turbo code as the error correction coding scheme. It outperforms convolutional code in large block size, but because of its time delay, it is often only used in the non-real-time service. In this paper, we discuss the encoder and decoder structure of turbo code in B3G mobile communication System. In addition, various decoding techniques, such as the Log-MAP, Max-log-MAP and SOVA algorithm for non-real-time service are deduced and compared. The performance results of decoder and algorithms in different configurations are also shown.
基金Supported by the Natural Science Research Foundation of Jiangsu Higher-Learning Insti-tution (No.04jkb510057).
文摘The encoding/decoding scheme based on Fiber Bragg Grating (FBG) for Optical Code Division Multiple Access (OCDMA) system is analyzed and the whole process from transmitting end to receiving end is researched in detail. The mathematical mode including signal transmission, summing, receiving and recovering are established respectively. One of the main sources of Bit Error Rate (BER) of OCDMA system based on FBGs is the unevenness of signal power spectrum, which leads to the chip powers unequal with each other. The Signal to Interfere Ratio (SIR) and BER performance of the system are studied and simulated at the case with uneven distribution of chips' powers.
基金supported by the Fundamental Research Funds for the Central Universities(FRF-TP20-062A1)Guangdong Basic and Applied Basic Research Foundation(2021A1515110070)。
文摘This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.
基金financially supported in part by National Key R&D Program of China(No.2018YFB1801402)in part by Huawei Technologies Co.,Ltd.
文摘In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete memoryless channels(BDMCs),the proposed decoders quantize the virtual subchannels of polar codes to maximize mutual information(MMI)between source bits and quantized symbols.The nested structure of polar codes ensures that the MMI quantization can be implemented stage by stage.Simulation results show that the proposed MMI decoders with 4 quantization bits outperform the existing nonuniform quantized decoders that minimize mean-squared error(MMSE)with 4 quantization bits,and yield even better performance than uniform MMI quantized decoders with 5 quantization bits.Furthermore,the proposed 5-bit quantized MMI decoders approach the floating-point decoders with negligible performance loss.
文摘A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.
文摘The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.
文摘A novel asynchronous ACS(add-compare-select) processor for Viterbi decoder is described.It is controlled by local handshake signals instead of the globe clock.The circuits of asynchronous adder unit,asynchronous comparator unit,and asynchronous selector unit are proposed.A full-custom design of asynchronous 4-bit ACS processor is fabricated in CSMC-HJ 0.6μm CMOS 2P2M mixed-mode process.At a supply voltage of 5V,when it operates at 20MHz,the power consumption is 75.5mW.The processor has no dynamic power consumption when it awaits an opportunity in sleep mode.The results of performance test of asynchronous 4-bit ACS processor show that the average case response time 19.18ns is only 82% of the worst-case response time 23.37ns.Compared with the synchronous 4-bit ACS processor in power consumption and performance by simulation,it reveals that the asynchronous ACS processor has some advantages than the synchronous one.
基金The Higher Education Technology Foundation of Huawei Technologies Co, Ltd (NoYJCB2005016WL)
文摘Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ratio （SNR） compared to the coherent case. To overcome the gap, an effective differential encoding and decoding scheme for multiband UWB systems is proposed. The proposed scheme employs the parallel concatenation of two recursive differential unitary space-frequency encoders at the transmitter. At the receiver, two component decoders iteratively decode information bits by interchanging soft metric values between each other. To reduce the computation complexity, a decoding algorithm which only uses transition probability to calculate the log likelihood ratios （LLRs） for the decoded bits is given. Simulation results show that the proposed scheme can dramatically outperform the conventional differential and even coherent detection at high SNR with a few iterations.
基金supported by the National Natural Science Foundation of China(NSFC)with project ID 62071498the Guangdong National Science Foundation(GDNSF)with project ID 2024A1515010213.
文摘Constituted by BCH component codes and its ordered statistics decoding(OSD),the successive cancellation list(SCL)decoding of U-UV structural codes can provide competent error-correction performance in the short-to-medium length regime.However,this list decoding complexity becomes formidable as the decoding output list size increases.This is primarily incurred by the OSD.Addressing this challenge,this paper proposes the low complexity SCL decoding through reducing the complexity of component code decoding,and pruning the redundant SCL decoding paths.For the former,an efficient skipping rule is introduced for the OSD so that the higher order decoding can be skipped when they are not possible to provide a more likely codeword candidate.It is further extended to the OSD variant,the box-andmatch algorithm(BMA),in facilitating the component code decoding.Moreover,through estimating the correlation distance lower bounds(CDLBs)of the component code decoding outputs,a path pruning(PP)-SCL decoding is proposed to further facilitate the decoding of U-UV codes.In particular,its integration with the improved OSD and BMA is discussed.Simulation results show that significant complexity reduction can be achieved.Consequently,the U-UV codes can outperform the cyclic redundancy check(CRC)-polar codes with a similar decoding complexity.
基金The National Natural Science Foundation of China(No.60871079)
文摘A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.
基金supported in part by National Natural Science Foundation of China through grant 61501002in part by Natural Science Project of Ministry of Education of Anhui through grant KJ2015A102+1 种基金in part by Talents Recruitment Program of Anhui Universityin part by the Key Laboratory Project of the Key Laboratory of Intelligent Computing and Signal Processing of the Ministry of Education of China, Anhui University
文摘This paper studies the decoding performance of low-density parity-check(LDPC)codes in a serial concatenation system with polar codes employing the successive cancellation(SC)decoding.It is known that the absolute incorrect log-likelihood ratio(LLR)values from the SC decoding can be very large.This phenomenon dramatically deteriorates the error correcting performance of the outer LDPC codes.In this paper,the LLR values of polar codes are regulated by a log processing before being sent to the LDPC decoder.Simulation results show that the log processing is an efficient approach with a low optimization complexity compared with the existing procedures to improve the performance of the serial concatenation systems.
基金The National High Technology Research and Develop-ment Program of China (863Program)(No.2006AA01Z264)the National Natural Science Foundation of China (No.60572072)
文摘Aiming at the optimum path excluding characteristics and the full constellation searching characteristics of the K-best detection algorithm, an improved-performance K-best detection algorithm and several reduced-complexity K-best detection algorithms are proposed. The improved-performance K-best detection algorithm deploys minimum mean square error （MMSE） filtering of a channel matrix before QR decomposition. This algorithm can decrease the probability of excluding the optimum path and achieve better performance. The reducedcomplexity K-best detection algorithms utilize a sphere decoding method to reduce searching constellation points. Simulation results show that the improved performance K-best detection algorithm obtains a 1 dB performance gain compared to the K- best detection algorithm based on sorted QR decomposition （SQRD）. Performance loss occurs when K = 4 in reduced complexity K-best detection algorithms. When K = 8, the reduced complexity K-best detection algorithms require less computational effort compared with traditional K-best detection algorithms and achieve the same performance.
文摘Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.
文摘A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.
