A model following adaptive control system for CSIM is presented in this paper. A dynamic mathematical model of slip control based system is obtained. With the help of model reducing technique, full order model is ...A model following adaptive control system for CSIM is presented in this paper. A dynamic mathematical model of slip control based system is obtained. With the help of model reducing technique, full order model is reduced to simplify the design without degrading much of the performance. Model following adaptive control laws in discrete form are derived. These laws satisfy the hyperstability condition for taking care of the load and machine parameter changes of the drive. A microprocessor 8098 is used to develop the speed controller. The implementation of the control system uses only available variables of the reference model and the controlled plant. Experimental results are given to demonstrate the good performance of the system.展开更多
Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management me...Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity 11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform.展开更多
A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of co...A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of constant current （CC） power supply could be changed according to transient physical state, and the variable down slope rate control could be used to ensure a stable welding process. The welding experiment results proved the effectiveness of this control approach.展开更多
The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an a...The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an additional automated system of unified templates necessary for the occurrence of “trainability” elements. The templates will be formed via a separate dedicated channel for transmission, processing and storage of the necessary information, not related to the operation of the terminal, with its subsequent visualization at the workplace of the duty personnel of traction substations, together with information from the “GID” software received via another dedicated wired channel. With the help of such a base of unified preset templates, in the future, it will be possible not only to identify the specific causes of each emergency shutdown but also to reduce their number by dynamically adjusting the existing presets of the standard operation algorithm.展开更多
This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed...This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.展开更多
In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is c...In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance.展开更多
We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss sta...We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss.展开更多
In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by usin...In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.展开更多
UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and t...UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and temperature correct are realized,The wavelength tuned output efficiency in the experiment is better than 97 %.展开更多
The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. R...The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. Real statistics on the number of microprocessor relay protection operations at the Buryatskaya traction substation are presented, simulation of the real train situation (in accordance with the regime maps of the throughput capacity of the sections of the Trans-Baikal railway) was carried out in the specialized software complex “KORTES”. Based on the results of the analysis of simulation modeling, the process of forming a unified template of settings using neural network technologies is considered, which characterizes only this specific regular train situation. To protect objects in the event of pre-emergency and emergency modes of operation of the traction power supply system, a variant of changing the standard operation algorithm of the TsZA-27.5-FKS (FTS) terminal by introducing additional blocks for calculating the predictive functions of current and voltage has been proposed.展开更多
This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filte...This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filter to remove these two normal noise signals. Signal from the MIT-BIH electrocardiogram database was used to test the performance of the filter. From the test results, the performance of the digital filer is reDT good. The filter coefficient is an integer number, therefore, the filtering algorithm can be successfully implemented on the microprocessor.展开更多
Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can ...Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can leak sensitive user data and information.This report will investigate microarchitecture vulnerabilities focusing on the Spectre and Meltdown exploits and will look at what they do,how they do it and,the real-world impact these vulnerabilities can cause.Additionally,there will be an introduction to the basic concepts of how several PC components operate to support this.展开更多
The paper introduces a temperature control systembased on AT89C51 single-chip-microprocessor, and discussesthe principle , hardware structure, and software design of thissystem in detail.
It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to sim...It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.展开更多
An experimental system is developed for the transient radiation effects testing of an anti-radiation hardened processor. Based on this system, the transient radiation effects in a microprocessor based on SPARC-V8 arch...An experimental system is developed for the transient radiation effects testing of an anti-radiation hardened processor. Based on this system, the transient radiation effects in a microprocessor based on SPARC-V8 architecture was investigated. The dose-rate-soft-error index parameters of the processor were determined according to the test results, as were the influences on the function and timing parameters of the processor. The power supply balance is affected, which caused the system to reset and be the main source of soft errors. The results showed the circuit recovery time is primarily determined by the internal PLL, while the core power and the output-low-IO ports are more sensitive to the transient dose rate effect. The power-integrity-hardened design is proposed to mitigate the transient radiation effect.展开更多
This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression struct...This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.展开更多
This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the...This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW,dynamic power of 385 nW @ 165 kHz,EDP 13 pJ/inst and the operating voltage of 350 mV are achieved.Under a light of about 150 kLux,the microprocessor can run at a rate of up to 500 kHz.The microprocessor can be used for wireless-sensor-network nodes展开更多
The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory ce...The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory cell is illustrated and then the comparison between the sensitive mapping and the layout of the circuit is made. A comparison result indicates that the area of the sensitive node in sensitive mapping is just the location of the drain in the layout. Therefore, SEE sensitivity in sensitive mapping fits well with that in the physical layout of functional units, which can directly and objectively indicate the size and distribution of sensitive areas. The investigation of sensitive mapping is a meaningful way to verify the hardened effect and provide a reference for improving hardened design by combining with the physical layout.展开更多
An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implemen...An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.展开更多
This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various ...This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various production rule systems.The methods of translating linguistically expressed rules into nu- merical representations are described and the hardware implementations are discussed.Finally,a parallel architecture for the inference microprocessor is presented.展开更多
文摘A model following adaptive control system for CSIM is presented in this paper. A dynamic mathematical model of slip control based system is obtained. With the help of model reducing technique, full order model is reduced to simplify the design without degrading much of the performance. Model following adaptive control laws in discrete form are derived. These laws satisfy the hyperstability condition for taking care of the load and machine parameter changes of the drive. A microprocessor 8098 is used to develop the speed controller. The implementation of the control system uses only available variables of the reference model and the controlled plant. Experimental results are given to demonstrate the good performance of the system.
文摘Virtual memory management is always a very essential issue of the modern microprocessor design. A memory management unit (MMU) is designed to implement a virtual machine for user programs, and provides a management mechanism between the operating system and user programs. This paper analyzes the tradeoffs considered in the MMU design of Unity 11 CPU of Peking University, and introduces in detail the solution of pure hardware table walking with two level page table organization. The implementation takes care of required operations and high performances needed by modern operating systems and low costs needed by embedded systems. This solution has been silicon proven, and successfully porting the Linux 2.4.17 kernel, the XWindow system, GNOME and most application software onto the Unity platform.
基金Supported by Research Project of Henan Science and Technology Foundation(0124110209,0211061900).
文摘A new kind of simple and flexible CO2 welding system was developed to carry out waveform control. The system consisted of IGBT inverter, PWM circuit and microprocessor unit （ MPU） , in which the output current of constant current （CC） power supply could be changed according to transient physical state, and the variable down slope rate control could be used to ensure a stable welding process. The welding experiment results proved the effectiveness of this control approach.
文摘The article discusses the possibility of further modernization of the standard microprocessor relay protection of AC overhead system feeders DPA-27.5-TNF, which is operated on the Trans-Baikal Railway by creating an additional automated system of unified templates necessary for the occurrence of “trainability” elements. The templates will be formed via a separate dedicated channel for transmission, processing and storage of the necessary information, not related to the operation of the terminal, with its subsequent visualization at the workplace of the duty personnel of traction substations, together with information from the “GID” software received via another dedicated wired channel. With the help of such a base of unified preset templates, in the future, it will be possible not only to identify the specific causes of each emergency shutdown but also to reduce their number by dynamically adjusting the existing presets of the standard operation algorithm.
文摘This paper introduces a SF vector control system of a slip frequency controlled induction mo-tor with simple structure,fair performance and convenient operation.It is realized by two singlechip microprocessors and fed from SPWM-GTR inverter.The whole system is combined by twosubsystems,both of them are 8031 single chip microprocessors.The communication between themis coordinated by the full duplex serial port within the chip and ask-and-answer communicationmanner.The error-corrected means adopted has improved the operation reliability of the system.A series of experimental results on a 3 kW induction motor are given at the end of this paper.
文摘In this paper the authors present an analysis and the implementation of microprocessor-baseddigital phase-locked loop speed control system for an induction motor which is actuated by aSPWM-GTR inverter.The system is controlled by a 16-bit single chip microprocessor.A new type of frequency and phase detector is presented in detail,An adaptive method isadopted in speed controller.A three mode control scheme is used.These techniques are very use-ful to the improvement of the dynamic behavior of digital AC motor drive system.Experimental results show that the system is of good stability,high precision and good dynam-ic performance.
基金The High Technology Research and Development Program of China (No.2006AA01Z226)the Natural Science Foundation of Hubei (No.2007ABD002)the Ministry of Education-INTEL Information Technology Foundation (No.MOE-INTEL-08-05)
文摘We propose a novel scheme, called on-line cache resizing （OCR）, to dynamically resize the cache and meet the size requirement of each application. At each periodic interval, the scheme gathers the cache hit-miss statistics at runtime using an extra tag array. These executing statistics serve as inputs to an analytical model of cache energy. The scheme uses energy as a primary metric to dynamically increase/decrease the number of active cache ways for the next interval. The scheme minimizes the active cache size to save energy with minimal performance loss. The simulation with SPEC 2000 benchmarks shows that OCR results in an average of 38.4% energy saving compared with fixed-size caches, with only 2.0% performance loss.
文摘In the era of Internet of Things, the battery life of edge devices must be extended for sensing connection to the Internet. We aim to reduce the power consumption of the microprocessor embedded in such devices by using a novel dynamically reconfigurable accelerator. Conventional microprocessors consume a large amount of power for memory access, in registers, and for the control of the processor itself rather than computation;this decreases the energy efficiency. Dynamically reconfigurable accelerators reduce such redundant power by computing in parallel on reconfigurable switches and processing element arrays (often consisting of an arithmetic logic unit (ALU) and registers). We propose a novel dynamically reconfigurable accelerator “DYNaSTA” composed of a dynamically reconfigurable data path and static ALU arrays. The static ALU arrays process instructions in parallel without registers and improve energy efficiency. The dynamically reconfigurable data path includes registers and many switches dynamically reconfigured to resolve operand dependencies between instructions mapped on the static ALU array, and forwards appropriate operands to the static ALU array. Therefore, the DYNaSTA accelerator has more flexibility while improving the energy efficiency compared with the conventional dynamically reconfigurable accelerators. We simulated the power consumption of the proposed DYNaSTA accelerator and measured the fabricated chip. As a result, the power consumption was reduced by 69% to 86%, and the energy efficiency improved 4.5 to 13 times compared to a general RISC microprocessor.
文摘UV wavelength auto-tuned tuned output system is realized by the difference method. Controlled by the microprocessor, output wavelength auto- tracking is achieved.Besides, equipment self-checking auto-positioning and temperature correct are realized,The wavelength tuned output efficiency in the experiment is better than 97 %.
文摘The article discusses the possibility of a potential reduction in the number of operations of microprocessor relay protection of feeders of the contact network of AC railways TsZA-27.5-FKS (FTS) for unknown reasons. Real statistics on the number of microprocessor relay protection operations at the Buryatskaya traction substation are presented, simulation of the real train situation (in accordance with the regime maps of the throughput capacity of the sections of the Trans-Baikal railway) was carried out in the specialized software complex “KORTES”. Based on the results of the analysis of simulation modeling, the process of forming a unified template of settings using neural network technologies is considered, which characterizes only this specific regular train situation. To protect objects in the event of pre-emergency and emergency modes of operation of the traction power supply system, a variant of changing the standard operation algorithm of the TsZA-27.5-FKS (FTS) terminal by introducing additional blocks for calculating the predictive functions of current and voltage has been proposed.
文摘This paper proposes a different method to eliminate base wander and power line interference in electrocardiogram, which introduces the integer coefficient filter theory and gives the detail for designing digital filter to remove these two normal noise signals. Signal from the MIT-BIH electrocardiogram database was used to test the performance of the filter. From the test results, the performance of the digital filer is reDT good. The filter coefficient is an integer number, therefore, the filtering algorithm can be successfully implemented on the microprocessor.
文摘Microprocessors such as those found in PCs and smartphones are complex in their design and nature.In recent years,an increasing number of security vulnerabilities have been found within these microprocessors that can leak sensitive user data and information.This report will investigate microarchitecture vulnerabilities focusing on the Spectre and Meltdown exploits and will look at what they do,how they do it and,the real-world impact these vulnerabilities can cause.Additionally,there will be an introduction to the basic concepts of how several PC components operate to support this.
文摘The paper introduces a temperature control systembased on AT89C51 single-chip-microprocessor, and discussesthe principle , hardware structure, and software design of thissystem in detail.
基金Supported by the National Natural Science Foundation of China for Distinguished Young Scholar under Grant No. 60325205 the National High Technology Development 863 Program of China under Grants No. 2002AA110010, No. 2005AA110010 No. 2005AA119020, and the National Grand Fundamental Research 973 Program of China under Grant No. 2005CB321600.
文摘It can be observed from looking backward that processor architecture is improved through spirally shifting from simple to complex and from complex to simple. Nowadays we are facing another shifting from complex to simple, and new innovative architecture will emerge to utilize the continuously increasing transistor budgets. The growing importance of wire delays, changing workloads, power consumption, and design/verification complexity will drive the forthcoming era of Chip Multiprocessors （CMPs）. Furthermore, typical CMP projects both from industries and from academics are investigated. Through going into depths for some primary theoretical and implementation problems of CMPs, the great challenges and opportunities to future CMPs are presented and discussed. Finally, the Godson series microprocessors designed in China are introduced.
文摘An experimental system is developed for the transient radiation effects testing of an anti-radiation hardened processor. Based on this system, the transient radiation effects in a microprocessor based on SPARC-V8 architecture was investigated. The dose-rate-soft-error index parameters of the processor were determined according to the test results, as were the influences on the function and timing parameters of the processor. The power supply balance is affected, which caused the system to reset and be the main source of soft errors. The results showed the circuit recovery time is primarily determined by the internal PLL, while the core power and the output-low-IO ports are more sensitive to the transient dose rate effect. The power-integrity-hardened design is proposed to mitigate the transient radiation effect.
基金This paper is supported in part by the National Natural Science Foundation of China under Grant Nos. 60633060, 60606008, 60776031, 60803031 and 90607010in part by the National Basic Research 973 Program of China under Grant Nos. 2005CB321604 and 2005CB321605in part by the National High Technology Research and Development 863 Program of China under Grant Nos. 2007AA01Z107, 2007AA01Z113, and 2007AA01Z476.
文摘This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.
基金Project supported by the National Natural Science Foundation of China(No.60906010)
文摘This paper presents an 8-bit sub-threshold microprocessor which can be powered by an integrated photosensitive diode.With a custom designed sub-threshold standard cell library and 1 kbit sub-threshold SRAM design, the leakage power of 58 nW,dynamic power of 385 nW @ 165 kHz,EDP 13 pJ/inst and the operating voltage of 350 mV are achieved.Under a light of about 150 kLux,the microprocessor can run at a rate of up to 500 kHz.The microprocessor can be used for wireless-sensor-network nodes
文摘The single event effects of the sensitivity of a circuit are investigated on a 32-bit microprocessor with a five-stage instruction pipeline by pulsed laser test. The investigation on sensitive mapping of the memory cell is illustrated and then the comparison between the sensitive mapping and the layout of the circuit is made. A comparison result indicates that the area of the sensitive node in sensitive mapping is just the location of the drain in the layout. Therefore, SEE sensitivity in sensitive mapping fits well with that in the physical layout of functional units, which can directly and objectively indicate the size and distribution of sensitive areas. The investigation of sensitive mapping is a meaningful way to verify the hardened effect and provide a reference for improving hardened design by combining with the physical layout.
文摘An optimization method of error detection and correction（EDAC） circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.
文摘This paper is concerned with the design of an inference microprocessor for production rule systems. Its implementation is based on both exact and inexact (fuzzy logic) reasoning,so it can he used for building various production rule systems.The methods of translating linguistically expressed rules into nu- merical representations are described and the hardware implementations are discussed.Finally,a parallel architecture for the inference microprocessor is presented.
