In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment syst...In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock;a performance increase of up to 16 times.展开更多
Encryption is used to secure sensitive computer data which may be at rest or in motion. There are several standard encryption algorithms that have been used to encrypt and protect blocks of sensitive data to ensure co...Encryption is used to secure sensitive computer data which may be at rest or in motion. There are several standard encryption algorithms that have been used to encrypt and protect blocks of sensitive data to ensure confidentiality. The most popular standard block encryption schemes are the Advanced Encryption Standard (AES), Triple Data Encryption Standard (3DES), and the first standardized encryption scheme, which is no longer the standard scheme now, namely the Data Encryption Standard (DES). AES is the current standard for block encryption used worldwide and is implemented on many processors. In this work, we compare the hardware performance of these three encryption schemes. First, we identified the underlying computational components for these three encryption schemes, and then we analyzed to what extent these computational components were being used in these block encryption schemes to encrypt and decrypt a given message. In this paper, we compared the contribution of these computational components to evaluate the overall encryption efficiency in terms of speed and computational delays for encrypting a given block of data for a given hardware platform. AES was found to be the faster scheme in terms of hardware computation speed in accomplishing the same encryption task compared to the other two block encryption schemes, namely, the DES and 3DES schemes.展开更多
The paper mainly discusses the integrity of the forwarded subscription message guaranteed by secure channel which encrypted in data communication by using data encryption standard （DES） algorithm and chaos code algo...The paper mainly discusses the integrity of the forwarded subscription message guaranteed by secure channel which encrypted in data communication by using data encryption standard （DES） algorithm and chaos code algorithm between broker nodes in the routing process of the contentbased publish/subscribe system. It analyzes the security of the secure channel encrypted with data communication by DES algorithm and chaos code algorithm, and finds out the secure channel can be easily attacked by known plain text. Therefore, the paper proposes the improved algorithm of message encryption and authentication, combining encryption and the generation of the message authentication code together to finish scanning at one time, which enhances both the secure degree and running efficiency. This secure channel system has a certain reference value to the pub/sub system requiring highly communication security.展开更多
After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end pro...After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end processor (FEP), encryption/decryption method and authentication protocol. Some other system-specific security measures are also proposed. Although these are examples only, the techniques discussed can also be used in and provide reference for other remote control systems.展开更多
The key generation algorithm of AES was introduced;the weaknesses of the key generation design of AES were investigated. According to the key demand put forward a kind of new design idea, and this designing strategy w...The key generation algorithm of AES was introduced;the weaknesses of the key generation design of AES were investigated. According to the key demand put forward a kind of new design idea, and this designing strategy was developed, which can be used to improve the key generation algorithm of AES. An analysis shows that such improvement can enhance the safety of the original algorithm without reducing its efficiency.展开更多
The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the ...The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal. In this paper, we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures. Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles. Using our laboratory-based power analysis system, we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard （3DES） hardware module in a real-life 32-bit CPU smart card. All 112 key bits of the 3DES were recovered with about 80 000 power traces.展开更多
文摘In cryptography, the Triple DES (3DES, TDES or officially TDEA) is a symmetric-key block cipher which applies the Data Encryption Standard (DES) cipher algorithm three times to each data block. Electronic payment systems are known to use the TDES scheme for the encryption/decryption of data, and hence faster implementations are of great significance. Field Programmable Gate Arrays (FPGAs) offer a new solution for optimizing the performance of applications meanwhile the Triple Data Encryption Standard (TDES) offers a mean to secure information. In this paper we present a pipelined implementation in VHDL, in Electronic Code Book (EBC) mode, of this commonly used cryptography scheme with aim to improve performance. We achieve a 48-stage pipeline depth by implementing a TDES key buffer and right rotations in the DES decryption key scheduler. Using the Altera Cyclone II FPGA as our platform, we design and verify the implementation with the EDA tools provided by Altera. We gather cost and throughput information from the synthesis and timing results and compare the performance of our design to common implementations presented in other literatures. Our design achieves a throughput of 3.2 Gbps with a 50 MHz clock;a performance increase of up to 16 times.
文摘Encryption is used to secure sensitive computer data which may be at rest or in motion. There are several standard encryption algorithms that have been used to encrypt and protect blocks of sensitive data to ensure confidentiality. The most popular standard block encryption schemes are the Advanced Encryption Standard (AES), Triple Data Encryption Standard (3DES), and the first standardized encryption scheme, which is no longer the standard scheme now, namely the Data Encryption Standard (DES). AES is the current standard for block encryption used worldwide and is implemented on many processors. In this work, we compare the hardware performance of these three encryption schemes. First, we identified the underlying computational components for these three encryption schemes, and then we analyzed to what extent these computational components were being used in these block encryption schemes to encrypt and decrypt a given message. In this paper, we compared the contribution of these computational components to evaluate the overall encryption efficiency in terms of speed and computational delays for encrypting a given block of data for a given hardware platform. AES was found to be the faster scheme in terms of hardware computation speed in accomplishing the same encryption task compared to the other two block encryption schemes, namely, the DES and 3DES schemes.
基金Supported by the National Natural Science Foun-dation of China (60273014)
文摘The paper mainly discusses the integrity of the forwarded subscription message guaranteed by secure channel which encrypted in data communication by using data encryption standard （DES） algorithm and chaos code algorithm between broker nodes in the routing process of the contentbased publish/subscribe system. It analyzes the security of the secure channel encrypted with data communication by DES algorithm and chaos code algorithm, and finds out the secure channel can be easily attacked by known plain text. Therefore, the paper proposes the improved algorithm of message encryption and authentication, combining encryption and the generation of the message authentication code together to finish scanning at one time, which enhances both the secure degree and running efficiency. This secure channel system has a certain reference value to the pub/sub system requiring highly communication security.
文摘After an introduction to the implementation of supervisory computer control (SCC) through networks and the relevant security issues, this paper centers on the core of network security design: intelligent front-end processor (FEP), encryption/decryption method and authentication protocol. Some other system-specific security measures are also proposed. Although these are examples only, the techniques discussed can also be used in and provide reference for other remote control systems.
文摘The key generation algorithm of AES was introduced;the weaknesses of the key generation design of AES were investigated. According to the key demand put forward a kind of new design idea, and this designing strategy was developed, which can be used to improve the key generation algorithm of AES. An analysis shows that such improvement can enhance the safety of the original algorithm without reducing its efficiency.
基金supported by the Major Program“Core of Electronic DevicesHigh-End General Chips+1 种基金and Basis of Software Products”of the Ministry of Industry and Information Technology of China(No.2014ZX01032205)the Key Technologies Research and Development Program of the Twelfth Five-Year Plan of China(No.MMJJ201401009)
文摘The security of CPU smart cards, which are widely used throughout China, is currently being threatened by side-channel analysis. Typical countermeasures to side-channel analysis involve adding noise and filtering the power consumption signal. In this paper, we integrate appropriate preprocessing methods with an improved attack strategy to generate a key recovery solution to the shortcomings of these countermeasures. Our proposed attack strategy improves the attack result by combining information leaked from two adjacent clock cycles. Using our laboratory-based power analysis system, we verified the proposed key recovery solution by performing a successful correlation power analysis on a Triple Data Encryption Standard （3DES） hardware module in a real-life 32-bit CPU smart card. All 112 key bits of the 3DES were recovered with about 80 000 power traces.
