Code acquisition is the kernel operation for signal synchronization in the spread-spectrum receiver.To reduce the computational complexity and latency of code acquisition,this paper proposes an efficient scheme employ...Code acquisition is the kernel operation for signal synchronization in the spread-spectrum receiver.To reduce the computational complexity and latency of code acquisition,this paper proposes an efficient scheme employing sparse Fourier transform(SFT)and the relevant hardware architecture for field programmable gate array(FPGA)and application-specific integrated circuit(ASIC)implementation.Efforts are made at both the algorithmic level and the implementation level to enable merged searching of code phase and Doppler frequency without incurring massive hardware expenditure.Compared with the existing code acquisition approaches,it is shown from theoretical analysis and experimental results that the proposed design can shorten processing latency and reduce hardware complexity without degrading the acquisition probability.展开更多
This paper presents the design of hardware and software of the house keeping system for a certain micro satellite. The system uses micro electronic technique, large scale integrated circuits, processors and computers ...This paper presents the design of hardware and software of the house keeping system for a certain micro satellite. The system uses micro electronic technique, large scale integrated circuits, processors and computers which has the advantages of strong function, high flexibility and reliability, It satisfies the requirements for efficient performance,light weight, small volume,and low consumption of power for micro satellite.展开更多
基金supported by the National Natural Science Foundation of China(61801503).
文摘Code acquisition is the kernel operation for signal synchronization in the spread-spectrum receiver.To reduce the computational complexity and latency of code acquisition,this paper proposes an efficient scheme employing sparse Fourier transform(SFT)and the relevant hardware architecture for field programmable gate array(FPGA)and application-specific integrated circuit(ASIC)implementation.Efforts are made at both the algorithmic level and the implementation level to enable merged searching of code phase and Doppler frequency without incurring massive hardware expenditure.Compared with the existing code acquisition approaches,it is shown from theoretical analysis and experimental results that the proposed design can shorten processing latency and reduce hardware complexity without degrading the acquisition probability.
文摘This paper presents the design of hardware and software of the house keeping system for a certain micro satellite. The system uses micro electronic technique, large scale integrated circuits, processors and computers which has the advantages of strong function, high flexibility and reliability, It satisfies the requirements for efficient performance,light weight, small volume,and low consumption of power for micro satellite.
