This paper proposes a new multi-stage parallel interference cancellation scheme by modifying the conventional multi-stage parallel interference canceller (PIC). At each stage, it first converts the interference-cancel...This paper proposes a new multi-stage parallel interference cancellation scheme by modifying the conventional multi-stage parallel interference canceller (PIC). At each stage, it first converts the interference-cancelled outputs from previous stage into thea prior information, in terms of which the bit mean values are computed and the multi-access interference (MAI) for each user is evaluated, and then an interference cancellation is performed to obtain further interference suppression. To reduce the implementation complexity, we give an approximation expression for bit mean value. The performance over AWGN channel is analyzed and compared to the conventional PIC. The user numberK=7 and spreading factorN=13 are chosen as simulation parameters. The computer simulation results show that the proposed PIC has better performance than the conventional PIC both with 2 interference cancellation (IC) stages, at bit error rate of 10?3, for example, about 3 dB performance gain is obtained by using the proposed PIC. It is also shown that our proposed PIC with 1-stage is superior to the conventional PIC with 2-stage in performance, which is of practical value because PIC with fewer stages can bring about shorter processing delay. Key words CDMA - parallel interference cancellation - multi-access interference CLC number TN 914 Foundation item: Supported by the National Natural Science Foundation of China (69772015)Biography: Xu Guo-xiong (1967-), male, Ph. D candidate, research direction: wireless communication.展开更多
In CDMA communication systems, all the subscribers share the common channel. The limitation factor on the system’s capacity is not the bandwidth, but multiuser interference and the near far problem. This paper models...In CDMA communication systems, all the subscribers share the common channel. The limitation factor on the system’s capacity is not the bandwidth, but multiuser interference and the near far problem. This paper models CDMA system from the perspective of mobile radio channels corrupted by additive white noise generated by multipath and multiple access interferences. The system’s receiver is assisted using different combining diversity techniques. Performance analysis of the system with these detection techniques is presented. The paper demonstrates that combining diversity techniques in the system’s receivers markedly improve the performance of CDMA systems.展开更多
A two-stage soft parallel interference cancellation (SPIC) algorithm in WCDMA system is proposed. The performance of the algorithm is analysed in perfect power control and near-far case, and the influence of the timin...A two-stage soft parallel interference cancellation (SPIC) algorithm in WCDMA system is proposed. The performance of the algorithm is analysed in perfect power control and near-far case, and the influence of the timing error on the system BER is discussed. Analysis and simulation show that the SPIC technique can enhance system capacity, and have a good ability to resist near-far impact. With its simple structure, it has good potential for practical applications.展开更多
A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel acce...A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...展开更多
随着SIMD（Single Instruction Multiple Data stream）结构DSP（Digital Signal Processor）片上集成了越来越多的处理单元,并行访存的灵活性及带宽效率对实际运算性能的影响越来越大.本文详细分析了一般SIMD结构DSP中基2 FFT（Fast Fo...随着SIMD（Single Instruction Multiple Data stream）结构DSP（Digital Signal Processor）片上集成了越来越多的处理单元,并行访存的灵活性及带宽效率对实际运算性能的影响越来越大.本文详细分析了一般SIMD结构DSP中基2 FFT（Fast Fourier Transform）并行算法面临的访存问题,采用简单的部分地址异或逻辑完成SIMD并行访存地址转换,实现了FFT运算的无冲突SIMD并行访存;提出了几种带特殊混洗模式的向量访存指令,可完全消除SIMD结构下基2FFT运算时需要的额外混洗指令操作.最后将其应用于某16路SIMD数字信号处理器YHFT-Matrix2中向量存储器VM的优化设计.测试结果表明,采用该SIMD并行存储结构优化的VM以增加18%的硬件开销实现了FFT运算全流水无冲突并行访存和100%并行访存带宽利用率;相比优化前的设计,不同点数FFT运算可获得1.32~2.66的加速比.展开更多
采用数字线索提示的目标觉察范式,以60名在校大学生与研究生为被试,设计3个实验探讨纯小数(整数部分是零的小数,例如0.2)的加工及其与空间表征的联系。实验1探讨纯小数作为线索时是否能引起空间注意的空间-数字反应编码联合效应(Spatial...采用数字线索提示的目标觉察范式,以60名在校大学生与研究生为被试,设计3个实验探讨纯小数(整数部分是零的小数,例如0.2)的加工及其与空间表征的联系。实验1探讨纯小数作为线索时是否能引起空间注意的空间-数字反应编码联合效应(Spatial Numerical Association of Response Codes,SNARC),结果发现,纯小数数量大小的加工可以引起空间注意的SNARC效应;实验2探讨纯小数的加工是否会同时激活小数点后对应的自然数,结果发现,对纯小数数量大小相同、小数点后对应的自然数是否有0(例如0.2和0.20,0.4和0.40)的加工能引起空间注意的转移;实验3比较纯小数的加工对纯小数本身及小数点后对应的自然数激活强度,结果发现,在纯小数数量大小判断和纯小数小数点后对应的自然数数量大小判断冲突的条件下,纯小数的加工未能引起注意的SNARC效应。该研究结果表明,在目标觉察范式中,纯小数的加工采取了平行通达的方式,引发了注意的SNARC效应,并且纯小数空间注意的转移受到纯小数本身以及对应的自然数的影响。展开更多
文摘This paper proposes a new multi-stage parallel interference cancellation scheme by modifying the conventional multi-stage parallel interference canceller (PIC). At each stage, it first converts the interference-cancelled outputs from previous stage into thea prior information, in terms of which the bit mean values are computed and the multi-access interference (MAI) for each user is evaluated, and then an interference cancellation is performed to obtain further interference suppression. To reduce the implementation complexity, we give an approximation expression for bit mean value. The performance over AWGN channel is analyzed and compared to the conventional PIC. The user numberK=7 and spreading factorN=13 are chosen as simulation parameters. The computer simulation results show that the proposed PIC has better performance than the conventional PIC both with 2 interference cancellation (IC) stages, at bit error rate of 10?3, for example, about 3 dB performance gain is obtained by using the proposed PIC. It is also shown that our proposed PIC with 1-stage is superior to the conventional PIC with 2-stage in performance, which is of practical value because PIC with fewer stages can bring about shorter processing delay. Key words CDMA - parallel interference cancellation - multi-access interference CLC number TN 914 Foundation item: Supported by the National Natural Science Foundation of China (69772015)Biography: Xu Guo-xiong (1967-), male, Ph. D candidate, research direction: wireless communication.
文摘In CDMA communication systems, all the subscribers share the common channel. The limitation factor on the system’s capacity is not the bandwidth, but multiuser interference and the near far problem. This paper models CDMA system from the perspective of mobile radio channels corrupted by additive white noise generated by multipath and multiple access interferences. The system’s receiver is assisted using different combining diversity techniques. Performance analysis of the system with these detection techniques is presented. The paper demonstrates that combining diversity techniques in the system’s receivers markedly improve the performance of CDMA systems.
文摘A two-stage soft parallel interference cancellation (SPIC) algorithm in WCDMA system is proposed. The performance of the algorithm is analysed in perfect power control and near-far case, and the influence of the timing error on the system BER is discussed. Analysis and simulation show that the SPIC technique can enhance system capacity, and have a good ability to resist near-far impact. With its simple structure, it has good potential for practical applications.
文摘A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented.For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.Simulation results indicate that by using sequential access,power reduction of 26% on a cache hit and 35% on a cache miss is achieved.High-speed approaches including modified current-mode sense amplifier and split dynamic tag comparators are adopted to achieve fast data access.Simulation results indicate that a typical clock to data access of 2.7ns is achieved...
文摘随着SIMD（Single Instruction Multiple Data stream）结构DSP（Digital Signal Processor）片上集成了越来越多的处理单元,并行访存的灵活性及带宽效率对实际运算性能的影响越来越大.本文详细分析了一般SIMD结构DSP中基2 FFT（Fast Fourier Transform）并行算法面临的访存问题,采用简单的部分地址异或逻辑完成SIMD并行访存地址转换,实现了FFT运算的无冲突SIMD并行访存;提出了几种带特殊混洗模式的向量访存指令,可完全消除SIMD结构下基2FFT运算时需要的额外混洗指令操作.最后将其应用于某16路SIMD数字信号处理器YHFT-Matrix2中向量存储器VM的优化设计.测试结果表明,采用该SIMD并行存储结构优化的VM以增加18%的硬件开销实现了FFT运算全流水无冲突并行访存和100%并行访存带宽利用率;相比优化前的设计,不同点数FFT运算可获得1.32~2.66的加速比.
文摘采用数字线索提示的目标觉察范式,以60名在校大学生与研究生为被试,设计3个实验探讨纯小数(整数部分是零的小数,例如0.2)的加工及其与空间表征的联系。实验1探讨纯小数作为线索时是否能引起空间注意的空间-数字反应编码联合效应(Spatial Numerical Association of Response Codes,SNARC),结果发现,纯小数数量大小的加工可以引起空间注意的SNARC效应;实验2探讨纯小数的加工是否会同时激活小数点后对应的自然数,结果发现,对纯小数数量大小相同、小数点后对应的自然数是否有0(例如0.2和0.20,0.4和0.40)的加工能引起空间注意的转移;实验3比较纯小数的加工对纯小数本身及小数点后对应的自然数激活强度,结果发现,在纯小数数量大小判断和纯小数小数点后对应的自然数数量大小判断冲突的条件下,纯小数的加工未能引起注意的SNARC效应。该研究结果表明,在目标觉察范式中,纯小数的加工采取了平行通达的方式,引发了注意的SNARC效应,并且纯小数空间注意的转移受到纯小数本身以及对应的自然数的影响。
