A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, wher...A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.展开更多
This paper studies the numerical simulation for semiconductor devices and discusses the software design of the simulation system. Our focus is on the deep submicron device simulation for BJT, MOSFET, heterojunction bi...This paper studies the numerical simulation for semiconductor devices and discusses the software design of the simulation system. Our focus is on the deep submicron device simulation for BJT, MOSFET, heterojunction bipolar transistors (HBT), etc. So the object oriented technology for software design and its realization is used to make the system easy to implement, maintain and extend. Besides the discussion of simulation and software system design, this paper introduces a device simulator SMDS and its parallel extension under local network environment using CORBA technology.展开更多
Single event transient of a real p-n junction in a 0.18μm bulk process is studied by 3D TCAD simulation. The impact of voltage, temperature, substrate concentration, and LET on SET is studied. Our simulation results ...Single event transient of a real p-n junction in a 0.18μm bulk process is studied by 3D TCAD simulation. The impact of voltage, temperature, substrate concentration, and LET on SET is studied. Our simulation results demonstrate that biases in the range 1.62 to 1.98V influence DSET current shape greatly and total collected charge weakly. Peak current and charge collection within 2ns decreases as temperature increases,and temperature has a stronger influence on SET currents than on total charge. Typical variation of substrate concentration in modern VDSM processes has a negligible effect on SEEs. Both peak current and total collection charge increases as LET increases.展开更多
文摘A direct tunneling model through gate dielectric s in CMOS devices in the frame of WKB approximation is reported.In the model,an im proved one-band effective mass approximation is used for the hole quantization, where valence band mixing is taken into account.By comparing to the experiments, the model is demonstrated to be applicable to both electron and hole tunneling c urrents in CMOS devices.The effect of the dispersion in oxide energy gap on the tunneling current is also studied.This model can be further extended to study th e direct tunneling current in future high-k materials.
文摘This paper studies the numerical simulation for semiconductor devices and discusses the software design of the simulation system. Our focus is on the deep submicron device simulation for BJT, MOSFET, heterojunction bipolar transistors (HBT), etc. So the object oriented technology for software design and its realization is used to make the system easy to implement, maintain and extend. Besides the discussion of simulation and software system design, this paper introduces a device simulator SMDS and its parallel extension under local network environment using CORBA technology.
文摘Single event transient of a real p-n junction in a 0.18μm bulk process is studied by 3D TCAD simulation. The impact of voltage, temperature, substrate concentration, and LET on SET is studied. Our simulation results demonstrate that biases in the range 1.62 to 1.98V influence DSET current shape greatly and total collected charge weakly. Peak current and charge collection within 2ns decreases as temperature increases,and temperature has a stronger influence on SET currents than on total charge. Typical variation of substrate concentration in modern VDSM processes has a negligible effect on SEEs. Both peak current and total collection charge increases as LET increases.
