在LTE(long term evolution)系统中对OFDM基带信号采样进行数字化处理时,随着系统带宽变化,采样速率也随之变化,但是根据协议,发送端采样速率固定,此时需要对信号进行过采样。通过对滤波器的分析比较以及仿真设计,得出结论,LTE系统中可...在LTE(long term evolution)系统中对OFDM基带信号采样进行数字化处理时,随着系统带宽变化,采样速率也随之变化,但是根据协议,发送端采样速率固定,此时需要对信号进行过采样。通过对滤波器的分析比较以及仿真设计,得出结论,LTE系统中可以使用半带滤波器实现信号的过采样。展开更多
Edge detection is a fundamental issue in image analysis. This paper proposes multirate algorithms for efficient implementation of edge detector, and a design example is illustrated.The multirate (decimation and/or int...Edge detection is a fundamental issue in image analysis. This paper proposes multirate algorithms for efficient implementation of edge detector, and a design example is illustrated.The multirate (decimation and/or interpolation) signal processing algorithms can achieve considerable savings in computation and storage. The proposed algorithms result in mapping relations of their z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase decomposition counterparts.The mapping properties can be readily utilized to efficiently analyze and synthesize multirate edge detection filters. The Very high-speed Hardware Description Language (VHDL) simulation results verify efficiency of the algorithms for real-time Field Programmable Gate-Array (FPGA)implementation.展开更多
文摘Edge detection is a fundamental issue in image analysis. This paper proposes multirate algorithms for efficient implementation of edge detector, and a design example is illustrated.The multirate (decimation and/or interpolation) signal processing algorithms can achieve considerable savings in computation and storage. The proposed algorithms result in mapping relations of their z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase decomposition counterparts.The mapping properties can be readily utilized to efficiently analyze and synthesize multirate edge detection filters. The Very high-speed Hardware Description Language (VHDL) simulation results verify efficiency of the algorithms for real-time Field Programmable Gate-Array (FPGA)implementation.
