In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding coun...In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding counter seeds are encoded by the specialized seed encoder and clock gating, the ineffective patterns do not act upon the circuit under test, these testing patterns are designed to form a pseudo single input change set, so as to lead to prominent decreases in power consumption and redundant testing patterns generated by different seeds, without losing stuck-at fault coverage. Experimental results based on ISCAS＇85 benchmark circuits demonstrate the efficiency of the approach.展开更多
基金supported by General Equipments Ministry for the Fore-research of Military Electronic Devices Technology in the 11th Five Plan(No.51323030406)
文摘In this paper, by using the folding counter and linear feedback shift register, a new vector generator is proosed. The decisive testing patterns are generated by using the selected fold distance. Then the folding counter seeds are encoded by the specialized seed encoder and clock gating, the ineffective patterns do not act upon the circuit under test, these testing patterns are designed to form a pseudo single input change set, so as to lead to prominent decreases in power consumption and redundant testing patterns generated by different seeds, without losing stuck-at fault coverage. Experimental results based on ISCAS＇85 benchmark circuits demonstrate the efficiency of the approach.
