A 0. 5mV high sensitivity,200Mbps CMOS limiting amplifier （LA） with 72dB ultra wide dynamic range is described. A novel active DC offset cancellation loop is elaborately analyzed and designed to achieve this perform...A 0. 5mV high sensitivity,200Mbps CMOS limiting amplifier （LA） with 72dB ultra wide dynamic range is described. A novel active DC offset cancellation loop is elaborately analyzed and designed to achieve this performance. Using a signal path, a received signal strength indicator （RSSI）, based on the piecewise-linear approximation, is realized with a ± 2dB logarithmic accuracy in a 60dB indicating range. The architecture of the LA and RSSI employed is determined by the optimal sensitivity and RSSI accuracy for a specified speed, gain, and power consumption. It consumes 60mW from a single 5V supply. The active area is 1.05mm^2 using standard 5V 0.6μm CMOS technology.展开更多
文摘A 0. 5mV high sensitivity,200Mbps CMOS limiting amplifier （LA） with 72dB ultra wide dynamic range is described. A novel active DC offset cancellation loop is elaborately analyzed and designed to achieve this performance. Using a signal path, a received signal strength indicator （RSSI）, based on the piecewise-linear approximation, is realized with a ± 2dB logarithmic accuracy in a 60dB indicating range. The architecture of the LA and RSSI employed is determined by the optimal sensitivity and RSSI accuracy for a specified speed, gain, and power consumption. It consumes 60mW from a single 5V supply. The active area is 1.05mm^2 using standard 5V 0.6μm CMOS technology.
