Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 fil...Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.展开更多
Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-ga...Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.展开更多
This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal...This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.展开更多
IGBT with high switching speed is described based on the dynamic controlled anode- short,which incorpo- rates a normally- on,p- MOSFET controlled by the anode voltage indirectly.This device works just as normal when ...IGBT with high switching speed is described based on the dynamic controlled anode- short,which incorpo- rates a normally- on,p- MOSFET controlled by the anode voltage indirectly.This device works just as normal when it is in on- state since the channel of the p- MOSFET is pinched- off.During the course of turning off,the channel of the p- MOSFET will prevent the injection of m inorities and introduce an extra access for the carriers to flow to the anode directly,which m akes the IGBT reach its off- state in a shorter time.The simulation results prove that the new structure can reduce the turn- off time by m ore than75 % compared with the normal one under the same break- down voltage and on- state perform ance.Only two more resistors are needed when using this structure,and the re- quirement of the drive circuits is just the sam e as normal.展开更多
GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold v...GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.展开更多
文摘Transparent zinc oxide thin film transistors （ZnO-TFTs） with bottom-gate and top-gate structures were constructed on 50mm silica glass substrates. The ZnO films were deposited by RF magnetron sputtering and SiO2 films served as the gate insulator layer. We found that the ZnO-TFTs with bottom-gate structure have better electrical performance than those with top-gate structure. The bottom-gate ZnO-TFTs operate as an n-channel enhancement mode, which have clear pinch off and saturation characteristics. The field effect mobility, threshold voltage, and the current on/off ratio were determined to be 18.4cm^2/（V ·s）, - 0. 5V and 10^4 , respectively. Meanwhile, the top-gate ZnO-TFTs exhibit n-chan- nel depletion mode operation and no saturation characteristics were detected. The electrical difference of the devices may be due to the different character of the interface between the channel and insulator layers. The two transistors types have high transparency in the visible light region.
文摘Based on the surface-gate and buried-gate structures,a novel buried-gate structure called the planar type buried-gate (PTBG) structure for static induction devices (SIDs) is proposed.An approach to realize a buried-gate type static induction transistor by conventional planar process technology is presented.Using this structure,it is successfully avoided the second epitaxy with a high degree of difficulty and the complicated mesa process in conventional buried gate.The experimental results demonstrate that this structure is desirable for application in power SIDs.Its advantages are high breakdown voltage and blocking gain.
基金TheNationalHighTechnologyResearchandDevelopmentProgramofChina (863Program ) (No .2 0 0 2AA1Z160 0 )
文摘This paper presents the design and the experimental measurements of two complementary metal-oxide-semiconductor (CMOS) LC-tuned voltage controlled oscillators (VCO) implemented in a 0.18 μm 6-metal-layer mixed-signal/RF CMOS technology. The design methodologies and approaches for the optimization of the ICs are presented. The first design is optimized for mixed-signal transistor, oscillated at 2.64 GHz with a phase noise of -93.5 dBc/Hz at 500 kHz offset. The second one optimized for RF transistor, using the same architecture, oscillated at 2.61 GHz with a phase noise of -95.8 dBc/Hz at 500 kHz offset. Under a 2 V supply, the power dissipation is 8 mW, and the maximum buffered output power for mixed-signal and RF transistor are -7 dBm and -5.4 dBm, respectively. Both kinds of oscillators make use of on-chip components only, allowing for simple and robust integration.
文摘IGBT with high switching speed is described based on the dynamic controlled anode- short,which incorpo- rates a normally- on,p- MOSFET controlled by the anode voltage indirectly.This device works just as normal when it is in on- state since the channel of the p- MOSFET is pinched- off.During the course of turning off,the channel of the p- MOSFET will prevent the injection of m inorities and introduce an extra access for the carriers to flow to the anode directly,which m akes the IGBT reach its off- state in a shorter time.The simulation results prove that the new structure can reduce the turn- off time by m ore than75 % compared with the normal one under the same break- down voltage and on- state perform ance.Only two more resistors are needed when using this structure,and the re- quirement of the drive circuits is just the sam e as normal.
文摘GeSi source/drain structure is purposefully adopted in SOI p MOSFET's to suppress the short channel effect (SCE).The impact of GeSi material (as source only,drain only or both source and drain) on the threshold voltage rolling off and DIBL effect is thoroughly investigated,as well as the influence of the Ge concentration and silicon film thickness.The Ge concentration should be carefully chosen as a tradeoff between the driving current and SCE improvement.The detailed physics is explained.
