本设计在Quartus II 11.0和NIOS II 11.0sp1 IDE开发环境下,以EP4CR6F17C8为核心,完成对全新工业级中文字库液晶显示器模块12864ZW的SOPC IP核的硬件架构和软核的驱动设计。完整的硬件构架和软件设计,实现了12864ZW液晶模块的字符、文...本设计在Quartus II 11.0和NIOS II 11.0sp1 IDE开发环境下,以EP4CR6F17C8为核心,完成对全新工业级中文字库液晶显示器模块12864ZW的SOPC IP核的硬件架构和软核的驱动设计。完整的硬件构架和软件设计,实现了12864ZW液晶模块的字符、文字和图片的显示。展开更多
The most popular hardware used for parallel depth migration is the PC-Cluster but its application is limited due to large space occupation and high power consumption. In this paper, we introduce a new hardware archite...The most popular hardware used for parallel depth migration is the PC-Cluster but its application is limited due to large space occupation and high power consumption. In this paper, we introduce a new hardware architecture, based on which the finite difference （FD） wavefield-continuation depth migration can be conducted using the Graphics Processing Unit （GPU） as a CPU coprocessor. We demonstrate the program module and three key optimization steps for implementing FD depth migration： memory, thread structure, and instruction optimizations and consider evaluation methods for the amount of optimization. 2D and 3D models are used to test depth migration on the GPU. The tested results show that the depth migration computational efficiency greatly increased using the general-purpose GPU, increasing by at least 25 times compared to the AMD 2.5 GHz CPU.展开更多
文摘本设计在Quartus II 11.0和NIOS II 11.0sp1 IDE开发环境下,以EP4CR6F17C8为核心,完成对全新工业级中文字库液晶显示器模块12864ZW的SOPC IP核的硬件架构和软核的驱动设计。完整的硬件构架和软件设计,实现了12864ZW液晶模块的字符、文字和图片的显示。
基金supported by the National Natural Science Foundation of China (Nos. 41104083 and 40804024) Fundamental Research Funds for the Central Universities (No, 2011YYL022)
文摘The most popular hardware used for parallel depth migration is the PC-Cluster but its application is limited due to large space occupation and high power consumption. In this paper, we introduce a new hardware architecture, based on which the finite difference （FD） wavefield-continuation depth migration can be conducted using the Graphics Processing Unit （GPU） as a CPU coprocessor. We demonstrate the program module and three key optimization steps for implementing FD depth migration： memory, thread structure, and instruction optimizations and consider evaluation methods for the amount of optimization. 2D and 3D models are used to test depth migration on the GPU. The tested results show that the depth migration computational efficiency greatly increased using the general-purpose GPU, increasing by at least 25 times compared to the AMD 2.5 GHz CPU.
