A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph...A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.展开更多
With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivota...With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivotal role in the practical applications of laser gyros.By analysis of the output signals from a laser gyro and an accelerometer,this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices.The design incorporates a finite impulse response(FIR)filter to process the gyro signal and employs a small-volume,impact-resistant quartz flexible accelerometer for signal aquisition.Simulation results demonstrate that the errors in X,Y,and Z axes fall within acceptable ranges while meeting filtering requirements.The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility,which provides an idea and method for optimizing performance and processing signals in laser gyro applications.展开更多
In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for impr...In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.展开更多
Based on the study of Walsh transformation,the zooming template of a two dimensional superimposure filter is decomposed and simplified,and it is real time implemented with FPGA.This method is simple and effective.Th...Based on the study of Walsh transformation,the zooming template of a two dimensional superimposure filter is decomposed and simplified,and it is real time implemented with FPGA.This method is simple and effective.The quality of the image is very good.展开更多
To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorit...To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.展开更多
Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process...Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.展开更多
A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this targe...ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.展开更多
Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of ...Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of electric appliances.The basic motivation of our solution is to utilize the collaboration among a mass of low-cost sensor nodes and actuator nodes to make life convenient.To achieve it,we design a novel system architecture with assembled component modules.In particular,we address some key technical challenges:1) Field-Programmable Gate Array (FPGA) Implementation of Adaptive Differential Pulse Code Modulation (ADPCM) for audio data;2) FPGA Implementation of Lempel Ziv Storer Szymanski (LZSS) for bulk data;3) combination of complex control logic.Finally,a set of experiments are presented to evaluate the performance of our solution.展开更多
Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out th...Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance （CSMA/CA）, develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language （VHDL）.展开更多
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A...To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.展开更多
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr...A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.展开更多
基金The National Natural Science Foundation of China(No.62401168,62401139,62401170)China Postdoctoral Science Foundation(No.2023MD744197)+2 种基金Postdoctoral Fellowship Program of CPSF(No.GZC20230631)Project for Enhancing Young and Middle-aged Teacher’s Research Basis Ability in Colleges of Guangxi(No.2023KY0218)Guangxi Key Laboratory Foundation of Optoelectronic Information Processing(No.GD23102)。
文摘A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication.
文摘With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivotal role in the practical applications of laser gyros.By analysis of the output signals from a laser gyro and an accelerometer,this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices.The design incorporates a finite impulse response(FIR)filter to process the gyro signal and employs a small-volume,impact-resistant quartz flexible accelerometer for signal aquisition.Simulation results demonstrate that the errors in X,Y,and Z axes fall within acceptable ranges while meeting filtering requirements.The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility,which provides an idea and method for optimizing performance and processing signals in laser gyro applications.
基金The National Natural Science Foundation of China (No.60974116)the Research Fund of Aeronautics Science (No. 20090869007)Specialized Research Fund for the Doctoral Program of Higher Education(No. 200802861063)
文摘In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.
基金Supported by National Nine-Five Project(No. 0 3 0 3 )
文摘Based on the study of Walsh transformation,the zooming template of a two dimensional superimposure filter is decomposed and simplified,and it is real time implemented with FPGA.This method is simple and effective.The quality of the image is very good.
基金The National High Technology Research and Development Program of China (863 Program)(No.2007AA01Z280)
文摘To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.
基金Project(2017YFC1405600)supported by the National Key R&D Program of ChinaProject(18JK05032)supported by the Scientific Research Project of Education Department of Shaanxi Province,China。
文摘Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified.
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
基金Supported by the National Natural Science Foundation of China (51176141)the Natural Science Foundation of Tianjin(11JCZDJC22500)
文摘ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity.
基金supported by the Natural Science Foundation of China under Grant No.61070206,No.61070205and No.60833009the National973Project of China under Grant No.2011CB302701+2 种基金the program of New Century Excellent Talents in University of China under Grant No.NCET-080737the Beijing National Natural Science Foundation under Grant No.4092030the Cosponsored Project of Beijing Committee of Education
文摘Wireless sensor-actuator networks can bring flexibility to smart home.We design and develop a smart home prototype using wireless sensor-actuator network technology to realize environmental sensing and the control of electric appliances.The basic motivation of our solution is to utilize the collaboration among a mass of low-cost sensor nodes and actuator nodes to make life convenient.To achieve it,we design a novel system architecture with assembled component modules.In particular,we address some key technical challenges:1) Field-Programmable Gate Array (FPGA) Implementation of Adaptive Differential Pulse Code Modulation (ADPCM) for audio data;2) FPGA Implementation of Lempel Ziv Storer Szymanski (LZSS) for bulk data;3) combination of complex control logic.Finally,a set of experiments are presented to evaluate the performance of our solution.
基金the National Natural Science Foundation of China
文摘Abstract： This work proposes a Field Programmable Gate Array （FPGA）-oriented architecture for the IEEE 802.11 Distributed Coordination Function （DCF） transceiver. We describe the functional blocks carrying out the Carrier Sense Multiple Accesses with Collision Avoidance （CSMA/CA）, develop the interfaces to the application layer and the physical layer, and implement it on FPGA devices by utilizing Very-high-speed-integrated-circuit Hardware Description Language （VHDL）.
基金Supported by the National Natural Science Foundation of China （No. 60576028） and the National High Technology Research and Development Program of China （No. 2007AA01Z2a5）
文摘To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural networks （ANN） hardware implementation methods, a bit-stream ANN construction method based on direct sigma-delta （Z-A） signal processing is presented. The bit-stream adder, multiplier and fully digital X-A modulator used in the bit-stream linear ANN are implemented in a field programmable gate array （FPGA）. A bit-stream linear ANN based on these bit-stream modules is presented and implemented. To verify the function and performance of the bit-stream linear ANN, the bit-stream adaptive predictor and the bit-stream adaptive noise cancellation system are presented. The predicted result of the bit-stream adaptive predictor is very close to the desired signal. Also, the bit-stream adaptive noise cancellation system removes the electric power noise effectively.
基金the Natural Science Foundation of Hubei Province (No.2005ABA301)
文摘A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance.
