A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in th...A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.展开更多
We report a back-gated metal-oxide-ferroelectric-metal （MOFM） field-effect transistor （FET） with lead zirconate titanate （PZT） material, in which an Al doped zinc oxide （AZO） channel layer with an optimized do...We report a back-gated metal-oxide-ferroelectric-metal （MOFM） field-effect transistor （FET） with lead zirconate titanate （PZT） material, in which an Al doped zinc oxide （AZO） channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm^2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.展开更多
We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for...We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).展开更多
0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insu...0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.展开更多
Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fie...Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fields.In order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally demonstrated.The phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm illumination.Besides,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance degradations.Additionally,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial recognition.Thisβ-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.展开更多
The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this w...The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET＇s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.展开更多
The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least...The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.展开更多
This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V...This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.展开更多
This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-...This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.展开更多
The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps intro...The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.展开更多
The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FET...The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FETs exhibit excellent performance. When Vds=2.5 V, the peak transconductance of the FETs is 0.396 μS, the average electron mobility is 50.17 cm2/（V·s）, the resistivity is 0.96 × 102 Ω·cm at Vgs = 0 V, and the current on/off ratio （Ion/Ioff） is approximately 105. ZnO NW-FET devices exposed to ultraviolet radiation （2.5 μW/cm2） exhibit punch-through and threshold voltage （Vth） shift （from-0.6 V to ＋0.7 V） and a decrease by almost half of the source-drain current （Ids, from 560 nA to 320 nA） due to drain-induced barrier lowering. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.展开更多
文摘A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.
基金Supported by the Fundamental Research Funds for the Central Universities of China
文摘We report a back-gated metal-oxide-ferroelectric-metal （MOFM） field-effect transistor （FET） with lead zirconate titanate （PZT） material, in which an Al doped zinc oxide （AZO） channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm^2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.
文摘We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).
基金the National Natural Science Foundation of China(No.60576051)the State Key Development Program for Basic Research of China(No.2006CB3027-01)~~
文摘0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.
基金supported by the National Natural Science Foundation of China(Nos.62027818,61874034,51861135105,and 51972319)International Science and Technology Cooperation Program of Shanghai Science and Technology Innovation Action Plan(No.21520713300)Science and Technology Commission of Shanghai Municipality(No.19520744400).
文摘Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fields.In order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally demonstrated.The phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm illumination.Besides,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance degradations.Additionally,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial recognition.Thisβ-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.
基金supported by the National Sciences and Technology Major Project 02
文摘The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET＇s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.
基金supported by the National Natural Science Foundation of China(No.60927006)the Major Projects of National Science and Technology
文摘The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.
文摘This paper reports that a novel type of suspended ZnO nanowire field-effect transistors （FETs） were successfully fabricated using a photolithography process, and their electrical properties were characterized by I-V measurements. Single-crystalline ZnO nanowires were synthesized by a hydrothermal method, they were used as a suspended ZnO nanowire channel of back-gate field-effect transistors （FET）. The fabricated suspended nanowire FETs showed a pchannel depletion mode, exhibited high on-off current ratio of -10^5. When VDS = 2.5V, the peak transconductances of the suspended FETs were 0.396 μS, the oxide capacitance was found to be 1.547 fF, the pinch-off voltage VTH was about 0.6 V, the electron mobility was on average 50.17cm2/Vs. The resistivity of the ZnO nanowire channel was estimated to be 0.96 × 10^2 Ω cm at VGS = 0 V. These characteristics revealed that the suspended nanowire FET fabricated by the photolithography process had excellent performance. Better contacts between the ZnO nanowire and metal electrodes could be improved through annealing and metal deposition using a focused ion beam.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906038)
文摘This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.
基金Project supported by the Major Fund for the National Science and Technology Program,China(No.2009ZX02306-04)the Fund of SOI Research and Development Center(No.20106250XXX)
文摘The mechanism of improving the TID radiation hardened ability of partially depleted silicon-oninsulator（SOI） devices by using the back-gate phosphorus ion implantation technology is studied. The electron traps introduced in Si O2 near back Si O2/Si interface by phosphorus ions implantation can offset positive trapped charges near the back-gate interface. The implanted high concentration phosphorus ions can greatly reduce the back-gate effect of a partially depleted SOI NMOS device, and anti-total-dose radiation ability can reach the level of 1 Mrad（Si） for experimental devices.
基金supported by the State Key Development Program for Basic Research of China(No.2002CB311901)the Director Fund of the Institute of Microelectronic of the Chinese Academy of Sciences (No.O8SB034002)the Pre-Research Fund of Weap on Equipment (No.6150105040)
文摘The fabrication and photoelectrical characteristics of suspended ZnO nanowire （NW） field-effect transistors （FETs） are presented. Single-crystal ZnO NWs are synthesized by a hydrothermal method. The fabricated FETs exhibit excellent performance. When Vds=2.5 V, the peak transconductance of the FETs is 0.396 μS, the average electron mobility is 50.17 cm2/（V·s）, the resistivity is 0.96 × 102 Ω·cm at Vgs = 0 V, and the current on/off ratio （Ion/Ioff） is approximately 105. ZnO NW-FET devices exposed to ultraviolet radiation （2.5 μW/cm2） exhibit punch-through and threshold voltage （Vth） shift （from-0.6 V to ＋0.7 V） and a decrease by almost half of the source-drain current （Ids, from 560 nA to 320 nA） due to drain-induced barrier lowering. Continued work is underway to reveal the intrinsic properties of suspended ZnO nanowires and to explore their device applications.
