A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is dis...A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.展开更多
Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modu...Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.展开更多
A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the pow...A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.展开更多
This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. T...This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.展开更多
A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplific...A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.展开更多
The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip,Si(Li),CdZnTe and CsI detectors,etc.,which can be further integrated the whole system and adopted to develop CMOS-bas...The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip,Si(Li),CdZnTe and CsI detectors,etc.,which can be further integrated the whole system and adopted to develop CMOS-based application,specific integrated circuit for Front End Electronics(FEE) of read-out system of nuclear physics,particle physics and astrophysics research,etc.It's why we used only CMOS transistor to develop the entire system.A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC4 filter,we perform shaping time in the range,465 ns to 2.76μs with a low output resistance and the linearity almost good.展开更多
A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching...A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.展开更多
In this letter,we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier(PA)in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA...In this letter,we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier(PA)in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA realizes an ultra-wideband CMOS PA in a small chip area.Wideband impedance matching is achieved with smaller chip dimension.The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA.The PA shows measured input return loss(<–10.8 dB)and output return loss(<–9.6 dB)in the entire bandwidth.A saturated output power of 22 dBm with maximum 20%power added efficiency(PAE)is also measured with the drain voltage at 5 V.The chip size is 0.44 mm^2 including all pads.展开更多
A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality...A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.展开更多
A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-...A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-bit resolution. The good perf or mance of S/H circuit benefits from the use of a newly designed regulated cascod e operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superi or to the operator amplifier of 60\|dB, 107\|MHz, 13 degree, and 33mW respective ly, which is used in the similar S/H circuit based on the 0.8 micron technology and designed by Michio Yotsuyanagi.展开更多
In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technol...In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.展开更多
A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the con...A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.展开更多
This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve th...This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.展开更多
高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通...高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通过优化电路结构和参数配置,结合了负反馈和级联放大器的优势,实现了较高的增益和性能指标。该运算放大器采用0.18 um CMOS工艺设计,仿真结果表明,在电压为1.8 V,负载电容为60 pF的环境下,该运算放大器的开环直流增益为81dB,增益带宽为110 M H z,相位裕度为72.9°,电源抑制比110 dB,电源总功耗仅为55 uW。大大提升了运放的增益,降低了电路的功耗并节省了面积。展开更多
文摘A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.
文摘Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.
文摘A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.
文摘This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.
基金The National High Technology Research and Development Program of China(863 Program)(No.2007AA01Z2A7)
文摘A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.
基金Support by the Third World Academy of Sciences (TWAS)the National Natural Science Foundation of China (No.10735060)
文摘The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip,Si(Li),CdZnTe and CsI detectors,etc.,which can be further integrated the whole system and adopted to develop CMOS-based application,specific integrated circuit for Front End Electronics(FEE) of read-out system of nuclear physics,particle physics and astrophysics research,etc.It's why we used only CMOS transistor to develop the entire system.A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC4 filter,we perform shaping time in the range,465 ns to 2.76μs with a low output resistance and the linearity almost good.
基金supported by the National Science & Technology Major Projects (No. 2012ZX03004008)by the National Natural Science Foundation of China (No. 61376082)by the Tianjin Natural Science Foundation (No. 13JCZDJC25900)
文摘A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.
基金supported by the National Natural Science Foundation of China(No.61841110)AoShan Talents Outstanding Scientist Program by Pilot National Laboratory for Marine Science and Technology(Qingdao)(No.2017ASTCP-OS03)。
文摘In this letter,we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier(PA)in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA realizes an ultra-wideband CMOS PA in a small chip area.Wideband impedance matching is achieved with smaller chip dimension.The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA.The PA shows measured input return loss(<–10.8 dB)and output return loss(<–9.6 dB)in the entire bandwidth.A saturated output power of 22 dBm with maximum 20%power added efficiency(PAE)is also measured with the drain voltage at 5 V.The chip size is 0.44 mm^2 including all pads.
基金Supported by the National High Technology Research and Development Program of China(“863”ProgramNo.2015AA01A703)
文摘A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.
文摘A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-bit resolution. The good perf or mance of S/H circuit benefits from the use of a newly designed regulated cascod e operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superi or to the operator amplifier of 60\|dB, 107\|MHz, 13 degree, and 33mW respective ly, which is used in the similar S/H circuit based on the 0.8 micron technology and designed by Michio Yotsuyanagi.
文摘In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.
文摘A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.
文摘This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.
文摘高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通过优化电路结构和参数配置,结合了负反馈和级联放大器的优势,实现了较高的增益和性能指标。该运算放大器采用0.18 um CMOS工艺设计,仿真结果表明,在电压为1.8 V,负载电容为60 pF的环境下,该运算放大器的开环直流增益为81dB,增益带宽为110 M H z,相位裕度为72.9°,电源抑制比110 dB,电源总功耗仅为55 uW。大大提升了运放的增益,降低了电路的功耗并节省了面积。
