An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate dela...An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.展开更多
A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (...A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.展开更多
A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained v...A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.展开更多
An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet ...An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.展开更多
In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal respon...In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal response. We present a new multiobjective genetic algorithm（MOGA） which uses a single objective sorting（SOS） method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Furthermore, we use a new method to calculate the lower bound of crosstalk. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.展开更多
We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to an...We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.展开更多
A k-shortest path based algorithm considering layout density and signal integrity for good buffer candidatelocations is proposed in this paper. Theoretical results for computing the maximal distance betweenbuffers are...A k-shortest path based algorithm considering layout density and signal integrity for good buffer candidatelocations is proposed in this paper. Theoretical results for computing the maximal distance betweenbuffers are derived under the timing, noise and slew rate constraints. By modifying the traditional uniformwire segmenting strategy and considering the impact of tile size on density penalty function, this work proposesk-shortest path algorithm to find the buffer insertion candidate locations. The experiments show thatthe buffers inserted can significantly optimize the design density, alleviate signal degradation, save thenumber of buffers inserted and the overall run time.展开更多
A uniform wire segmentation algorithm for performance optimization of distributed RLC interconnects was proposed in this paper. The optimal wire length for identical segments and buffer size for buffer inser-tion are ...A uniform wire segmentation algorithm for performance optimization of distributed RLC interconnects was proposed in this paper. The optimal wire length for identical segments and buffer size for buffer inser-tion are obtained through computation and derivation, based on a 2-pole approximatian model of distribut-ed RLC interconnect. For typical inductance value and long wires under 180nm technology, experiments show that the uniform wire segmentation technique proposed in the paper can reduce delay by about 27%～56%, while requires 34%～69% less total buffer usage and thus 29% to 58% less power consump-tion. It is suitable for long RLC interconnect performance optimization.展开更多
When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to proce...When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.展开更多
With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provid...With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.展开更多
文摘An algorithm of path based timing optimization by buffer insertion is presented.The algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look up table for gate delay estimation.And heuristic method of buffer insertion is presented to reduce delay.The algorithm is tested by industral circuit case.Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
基金The National Natural Science Foundation of China (No. 90307017)
文摘A new approach was proposed to construct a performance-driven rectilinear Steiner tree with simultaneous buffer insertion and wiresizing optimization (PDRST/BW) under a higher order resistance-inductance-capacitance (RLC) delay model. This approach is based on the concept of sharing-buffer insertion and dynamic programming approach combined with a bottom-up rectilinear Steiner tree construction. The performances include the timing delay and the quality of signal waveform. The experimental results show that our proposed approach is scalable and obtains better performance than SP-tree and graph-RTBW approaches for the test signal nets.
文摘A path-based timing optimization algorithm for buffer insertion and simultaneous sizing is proposed. Firstly, candidate buffer insertion location and buffer size for each branch in a given routing path were obtained via localized timing optimization. Then, through evaluating each potential insertion against design objectives, potential optimal buffer insertion locations and sizes for the whole routing tree were determined. At last, by removing redundant buffer insertion operations which do not maximize S （ so ）, given timing requirements are finally fulfilled through minimum number of buffers.
文摘An algorithm of minimizing the number of buffers under certain delay constraint with accurate delay models is presented.Given a two-terminal net,the algorithm can minimize the total number of buffers inserted to meet the delay constraint.A high order delay model is applied to estimate interconnect delay and a nonlinear delay model based on look-up table is for buffer delay estimation.The experimental results show that the algorithm can efficiently achieve the trade-offs between number of buffers and delay,and avoid needless power and area cost.The running time is satisfactory.
基金Supported by the National Natural Science Foundation of China (90307017)
文摘In this paper, we study the interconnect buffer and wiresizing optimization problem under a distributed RLC model to optimize not just area and delay, but also crosstalk for RLC circuit with non-monotone signal response. We present a new multiobjective genetic algorithm（MOGA） which uses a single objective sorting（SOS） method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Furthermore, we use a new method to calculate the lower bound of crosstalk. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.
文摘We present a staggered buffer connection method that provides flexibility for buffer insertion while designing global signal networks using the tile-based FPGA design methodology. An exhaustive algorithm is used to analyze the trade-off between area and speed of the global signal networks for this staggered buffer insertion scheme, and the criterion for determining the design parameters is presented. The comparative analytic result shows that the methods in this paper are proven to be more efficient for FPGAs with a large array size.
基金Supported by the National Key Project of Scientific and Technical Supporting Programs (No. 2006BAK07B04).
文摘A k-shortest path based algorithm considering layout density and signal integrity for good buffer candidatelocations is proposed in this paper. Theoretical results for computing the maximal distance betweenbuffers are derived under the timing, noise and slew rate constraints. By modifying the traditional uniformwire segmenting strategy and considering the impact of tile size on density penalty function, this work proposesk-shortest path algorithm to find the buffer insertion candidate locations. The experiments show thatthe buffers inserted can significantly optimize the design density, alleviate signal degradation, save thenumber of buffers inserted and the overall run time.
文摘A uniform wire segmentation algorithm for performance optimization of distributed RLC interconnects was proposed in this paper. The optimal wire length for identical segments and buffer size for buffer inser-tion are obtained through computation and derivation, based on a 2-pole approximatian model of distribut-ed RLC interconnect. For typical inductance value and long wires under 180nm technology, experiments show that the uniform wire segmentation technique proposed in the paper can reduce delay by about 27%～56%, while requires 34%～69% less total buffer usage and thus 29% to 58% less power consump-tion. It is suitable for long RLC interconnect performance optimization.
基金the 863 National Hi-Tech Research and Development Plan of China(Grant No.2005AA1Z1230) the National Natural Science Foundation ofChina(Grant No.90307017).
文摘When IC technology is scaled into the very deep sub-micron regime, the optical proximity effects （OPE） turn into noticeable in optical lithography. Consequently, clock skew becomes more and more susceptible to process variations, such as OPE. In this paper, we propose a new buffered clock tree routing algorithm to prevent the influence of OPE and process variations to clock skew. Based on the concept of BSF （branch sensitivity factor）, our algorithm manages to reduce the skew sensitivity of the clock tree in the topology generation. The worst case skew due to the wire width change has been estimated, and proper buffers are inserted to avoid large capacitance load. Experimental results show that our algorithm can produce a more reliable, processinsensitive clock tree, and control clock skews in their permissible range evidently.
文摘With the rapid development of deep submicron (DSM) VLSI circuit designs, many issues such as time closure and power consumption are making the physical designs more and more challenging. In this review paper we provide readers with some recent progress of the VLSI physical designs. The recent developments of floorplanning and placement, interconnect effects, modeling and delay, buffer insertion and wire sizing, circuit order reduction, power grid analysis, parasitic extraction, and clock signal distribution are briefly reviewed.
