Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption S...Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.展开更多
A dynamically reconfigurable system can change its configuration during operation, and studies of such systems are being carried out in many fields. In particular, medical technology and aerospace engineering must ens...A dynamically reconfigurable system can change its configuration during operation, and studies of such systems are being carried out in many fields. In particular, medical technology and aerospace engineering must ensure system safety because any defect will have serious consequences. Model checking is a method for verifying system safety. In this paper, we propose the Dynamic Linear Hybrid Automaton (DLHA) specification language and show a method to analyze reachability for a system consisting of several DLHAs.展开更多
This paper describes specific constraints of vision systems that are dedicated to be embedded in mobile robots. If PC-based hardware architecture is convenient in this field because of its versatility, flexibility, pe...This paper describes specific constraints of vision systems that are dedicated to be embedded in mobile robots. If PC-based hardware architecture is convenient in this field because of its versatility, flexibility, performance, and cost, current real-time operating systems are not completely adapted to long processing with varying duration, and it is often necessary to oversize the system to guarantee fail-safe functioning. Also, interactions with other robotic tasks having more priority are difficult to handle. To answer this problem, we have developed a dynamically reconfigurable vision processing system, based on the innovative features of Cleopatre real-time applicative layer concerning scheduling and fault tolerance. This framework allows to define emergency and optional tasks to ensure a minimal quality of service for the other subsystems of the robot, while allowing to adapt dynamically vision processing chain to an exceptional overlasting vision process or processor overload. Thus, it allows a better cohabitation of several subsystems in a single hardware, and to develop less expensive but safe systems, as they will be designed for the regular case and not rare exceptional ones. Finally, it brings a new way to think and develop vision systems, with pairs of complementary operators.展开更多
Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video...Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal<span> and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, </span><i><span>i.e.</span></i><span>, configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm</span><sup><span style="vertical-align:super;">2</span></sup><span> and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.</span>展开更多
While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one wa...While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.展开更多
Based on the flexible quadtree partition structure of coding tree units(CTUs),the deblocking filter(DBF)in high efficiency video coding(HEVC)consumes a lot of resources when implemen-ted by hardware.It is difficult to...Based on the flexible quadtree partition structure of coding tree units(CTUs),the deblocking filter(DBF)in high efficiency video coding(HEVC)consumes a lot of resources when implemen-ted by hardware.It is difficult to achieve flexible switching between different sizes of coding blocks.Aiming at this problem,a reconfigurable implementation of DBF is proposed.Based on the dynamic programmable reconfigurable video array processor(DPRAP)with context switch reconfiguration mechanism,the runtime flexible switching of two coding block sizes is realized.The experimental results show that the highest work-frequency reaches 151.4 MHz.Compared with the dedicated hardware architecture scheme,the resource consumption can be reduced by 28.1%while realizing the dynamic switching between algorithms of two coding block sizes.Compared with the results of HM16.0,by using a complete I-frame for testing,the average peak signal-to-noise ratio(PSNR)of the reconfigurable implementation proposed in this paper has increased by 3.0508 dB,the coding quality has improved to a certain extent.展开更多
The concept of unmanned weapon system-of-systems(UWSoS)involves a collection of various unmanned systems to achieve or accomplish a specific goal or mission.The mission reliability of UWSoS is represented by its abili...The concept of unmanned weapon system-of-systems(UWSoS)involves a collection of various unmanned systems to achieve or accomplish a specific goal or mission.The mission reliability of UWSoS is represented by its ability to finish a required mission above the baselines of a given mission.However,issues with heterogeneity,cooperation between systems,and the emergence of UWSoS cannot be effectively solved by traditional system reliability methods.This study proposes an effective operation-loop-based mission reliability evaluation method for UWSoS by analyzing dynamic reconfiguration.First,we present a new connotation of an effective operation loop by considering the allocation of operational entities and physical resource constraints.Then,we propose an effective operationloop-based mission reliability model for a heterogeneous UWSoS according to the mission baseline.Moreover,a mission reliability evaluation algorithm is proposed under random external shocks and topology reconfiguration,revealing the evolution law of the effective operation loop and mission reliability.Finally,a typical 60-unmanned-aerial-vehicle-swarm is taken as an example to demonstrate the proposed models and methods.The mission reliability is achieved by considering external shocks,which can serve as a reference for evaluating and improving the effectiveness of UWSoS.展开更多
The Rate Distortion Optimization(RDO)algorithm in High Efficiency Video Coding(HEVC)has many iterations and a large number of calculations.In order to decrease the calculation time and meet the requirements of fast sw...The Rate Distortion Optimization(RDO)algorithm in High Efficiency Video Coding(HEVC)has many iterations and a large number of calculations.In order to decrease the calculation time and meet the requirements of fast switching of RDO algorithms of different scales,an RDO dynamic reconfigurable structure is proposed.First,the Quantization Parameter(QP)and bit rate values were loaded through an H⁃tree Configurable Network(HCN),and the execution status of the array was detected in real time.When the switching request of the RDO algorithm was detected,the corresponding configuration information was delivered.This self⁃reconfiguration implementation method improved the flexibility and utilization of hardware.Experimental results show that when the control bit width was only increased by 31.25%,the designed configuration network could increase the number of controllable processing units by 32 times,and the execution cycle was 50%lower than the same type of design.Compared with previous RDO algorithm,the RDO algorithm implemented on the reconfigurable array based on the configuration network had an average operating frequency increase of 12.5%and an area reduction of 56.4%.展开更多
Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for...Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.展开更多
Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or ...Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.展开更多
As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of task...As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.展开更多
With the construction of the power Internet of Things(IoT),communication between smart devices in urban distribution networks has been gradually moving towards high speed,high compatibility,and low latency,which provi...With the construction of the power Internet of Things(IoT),communication between smart devices in urban distribution networks has been gradually moving towards high speed,high compatibility,and low latency,which provides reliable support for reconfiguration optimization in urban distribution networks.Thus,this study proposed a deep reinforcement learning based multi-level dynamic reconfiguration method for urban distribution networks in a cloud-edge collaboration architecture to obtain a real-time optimal multi-level dynamic reconfiguration solution.First,the multi-level dynamic reconfiguration method was discussed,which included feeder-,transformer-,and substation-levels.Subsequently,the multi-agent system was combined with the cloud-edge collaboration architecture to build a deep reinforcement learning model for multi-level dynamic reconfiguration in an urban distribution network.The cloud-edge collaboration architecture can effectively support the multi-agent system to conduct“centralized training and decentralized execution”operation modes and improve the learning efficiency of the model.Thereafter,for a multi-agent system,this study adopted a combination of offline and online learning to endow the model with the ability to realize automatic optimization and updation of the strategy.In the offline learning phase,a Q-learning-based multi-agent conservative Q-learning(MACQL)algorithm was proposed to stabilize the learning results and reduce the risk of the next online learning phase.In the online learning phase,a multi-agent deep deterministic policy gradient(MADDPG)algorithm based on policy gradients was proposed to explore the action space and update the experience pool.Finally,the effectiveness of the proposed method was verified through a simulation analysis of a real-world 445-node system.展开更多
Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array(FPGA). Discussed are the dynamic reconfiguration principles and methods. Proposed is a global...Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array(FPGA). Discussed are the dynamic reconfiguration principles and methods. Proposed is a global dynamic reconfiguration scheme using Xilinx FPGA and platform flash. Using the revision capabilities of Xilinx XCF32P platform flash, an artificial neural network based on Xilinx XC2V30P Virtex-Ⅱ can be reconfigured dynamically from back propagation(BP) learning algorithms to BP network testing algorithms. The experimental results indicate that the scheme is feasible, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably.展开更多
The dynamic reconfiguration technique based on field-programmable gate array （FPGA） can improve the resource utilization. Discussed are the dynamic reconfiguration principles and methods. Proposed is a remote dynami...The dynamic reconfiguration technique based on field-programmable gate array （FPGA） can improve the resource utilization. Discussed are the dynamic reconfiguration principles and methods. Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-Ⅱ FPGA and SMCS Ethernet Physical layer transceiver（PHY）. The hardware of the system is designed with Xilinx Virtex-U XC2V30P FPGA that embedds MicroBlaze and MAC IP core, and its network communication software based on transmission control protoeol/Internet protocol （TCP/IP） protocol is programmed by loading LwIP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system（RFDRS） can switch freely in the eight lighting modes of light emitting diodes （LED）, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably, which is advantageous in the system upgrade and software update.展开更多
This paper deals with reduction of losses in electric power distribution system through a dynamic reconfiguration case study of a grid in the city of Mostar,Bosnia and Herzegovina.The proposed solution is based on a n...This paper deals with reduction of losses in electric power distribution system through a dynamic reconfiguration case study of a grid in the city of Mostar,Bosnia and Herzegovina.The proposed solution is based on a nonlinear model predictive control algorithm which determines the optimal switching operations of the distribution system.The goal of the control algorithm is to find the optimal radial network topology which minimizes cumulative active power losses and maximizes voltages across the network while simultaneously satisfying all system constraints.The optimization results are validated through multiple simulations(using real power demand data collected for a few characteristic days during winter and summer)which demonstrate the efficiency and usefulness of the developed control algorithm in reducing the grid losses by up to 14%.展开更多
This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data...This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine （FSM） controllers. Each cluster contains various kinds of ceils that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.展开更多
This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications,particularly for Internet of things(IoT)devices.The architecture enables runtime dynamic recon...This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications,particularly for Internet of things(IoT)devices.The architecture enables runtime dynamic reconfiguration of the datapath,allowing efficient balancing between computational performance and power consumption.This is achieved through interchangeable components and clock gating mechanisms,which help the processor adapt to varying workloads.A prototype of the architecture was implemented on a Xilinx Artix 7 field programmable gate array(FPGA).Experimental results show significant improvements in power efficiency and performance.The mini configuration achieves an impressive reduction in power consumption,using only 36%of the baseline power.Meanwhile,the full configuration boosts performance by 8%over the baseline.The flexible and adaptable nature of this architecture makes it highly suitable for a wide range of low-power IoT applications,providing an effective solution to meet the growing demands for energy efficiency in modern IoT devices.展开更多
Continuous development of photonic crystals(PCs)over the last 30 years has carved out many new scientific frontiers.However,creating tunable PCs that enable flexible control of geometric configurations remains a chall...Continuous development of photonic crystals(PCs)over the last 30 years has carved out many new scientific frontiers.However,creating tunable PCs that enable flexible control of geometric configurations remains a challenge.Here we present a scheme to produce a tunable plasma photonic crystal(PPC)‘kaleidoscope’with rich diversity of structural configurations in dielectric barrier discharge.Multi-freedom control of the PPCs,including the symmetry,dielectric constant,crystal orientation,lattice constant,topological state,and structures of scattering elements,has been realized.Four types of lattice reconfigurations are demonstrated,including transitions from periodic to periodic,disordered to ordered,non-topological to topological,and striped to honeycomb Moirélattices.Furthermore,alterations in photonic band structures corresponding to the reconstruction of various PPCs have been investigated.Our system presents a promising platform for generating a PPC‘kaleidoscope’,offering benefits such as reduced equipment requirements,low cost,rapid response,and enhanced flexibility.This development opens up new opportunities for both fundamental and applied research.展开更多
As aerospace vehicles travel in a hellish environment, the reliability of the measuring and controlling systems has played a critical role in the credibility of a whole airborne system. Embryo-electronic system is a b...As aerospace vehicles travel in a hellish environment, the reliability of the measuring and controlling systems has played a critical role in the credibility of a whole airborne system. Embryo-electronic system is a bionic hardware capable of self-diagnosing and self-healing. This article presents a new approach to design embryo-electronic systems and introduces their bionic principles, system structures and fanlt-tolerant mechanism. As the current methods cannot meet the requirements for large-scale embryo-electronic systems, this article advances a new shift-register-based configuration memory of embryonic system to solve the problem by using the inter-cell communication to reduce the gene storage capacity of a single cell. The article designs an overall structure of the shift-register-based configuration memories of the embryonic system and connects them into a chain structure. The article also designs an inner circuit of the cell, the control of shift-register-based configuration memory and the way of runtime dynamic configuration. The simulation of field programmable gate array （FPGA） evidences the realizability of the proposed design. Compared to the SRAM-based one, this memory can save 90% of the area when constructing embryonic systems larger than 128× 128 under the same condition.展开更多
The increasing integration of photovoltaic generators(PVGs) and the uneven economic development in different regions may cause the unbalanced spatial-temporal distribution of load demands in an urban distribution netw...The increasing integration of photovoltaic generators(PVGs) and the uneven economic development in different regions may cause the unbalanced spatial-temporal distribution of load demands in an urban distribution network(UDN). This may lead to undesired consequences, including PVG curtailment, load shedding, and equipment inefficiency, etc. Global dynamic reconfiguration provides a promising method to solve those challenges. However, the power flow transfer capabilities for different kinds of switches are diverse, and the willingness of distribution system operators(DSOs) to select them is also different. In this paper, we formulate a multi-objective dynamic reconfiguration optimization model suitable for multi-level switching modes to minimize the operation cost, load imbalance, and the PVG curtailment. The multi-level switching includes feeder-level switching, transformer-level switching, and substation-level switching. A novel load balancing index is devised to quantify the global load balancing degree at different levels. Then, a stochastic programming model based on selected scenarios is established to address the uncertainties of PVGs and loads. Afterward, the fuzzy c-means(FCMs) clustering is applied to divide the time periods of reconfiguration. Furthermore, the modified binary particle swarm optimization(BPSO)and Cplex solver are combined to solve the proposed mixed-integer second-order cone programming(MISOCP) model. Numerical results based on the 148-node and 297-node systems are obtained to validate the effectiveness of the proposed method.展开更多
基金Supported by the National Natural Science Foun-dation of China (60374008)
文摘Reconfigurable computing has grown to become an important and large field of research, it offers advantages over traditional hardware and software implementations of computational algorithms. The Advanced Encryption Standard （AES） algorithm is widely applied in government department and commerce. This paper analyzed the AES algorithms with different cipher keys, adopted a novel key scheduler that generated the round key real-time, proposed a dynamically reconfigurable encryption system which supported the AES algorithm with different cipher keys, and designed the architecture of the reconfigurable system. The dynamically reconfigurable AES system had been realized on FPGA. The result proves that the reconfigurable AES system is flexible, lower cost and high security level.
文摘A dynamically reconfigurable system can change its configuration during operation, and studies of such systems are being carried out in many fields. In particular, medical technology and aerospace engineering must ensure system safety because any defect will have serious consequences. Model checking is a method for verifying system safety. In this paper, we propose the Dynamic Linear Hybrid Automaton (DLHA) specification language and show a method to analyze reachability for a system consisting of several DLHAs.
基金This work was supported by the French research office(No.01 K 0742)under the Cléopatre project.
文摘This paper describes specific constraints of vision systems that are dedicated to be embedded in mobile robots. If PC-based hardware architecture is convenient in this field because of its versatility, flexibility, performance, and cost, current real-time operating systems are not completely adapted to long processing with varying duration, and it is often necessary to oversize the system to guarantee fail-safe functioning. Also, interactions with other robotic tasks having more priority are difficult to handle. To answer this problem, we have developed a dynamically reconfigurable vision processing system, based on the innovative features of Cleopatre real-time applicative layer concerning scheduling and fault tolerance. This framework allows to define emergency and optional tasks to ensure a minimal quality of service for the other subsystems of the robot, while allowing to adapt dynamically vision processing chain to an exceptional overlasting vision process or processor overload. Thus, it allows a better cohabitation of several subsystems in a single hardware, and to develop less expensive but safe systems, as they will be designed for the regular case and not rare exceptional ones. Finally, it brings a new way to think and develop vision systems, with pairs of complementary operators.
文摘Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal<span> and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, </span><i><span>i.e.</span></i><span>, configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm</span><sup><span style="vertical-align:super;">2</span></sup><span> and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.</span>
文摘While some applications in memory can be constrained by memory bandwidth and memory cost, this paper proposes a transformation of the application into a one-bit FSM. When the finite state machine is very large, one way to improve the area and delay efficiently is to break down the large finite state machine into many smaller machines. The area efficiency can be improved if fewer machines are active simultaneously in the pipelined architecture. This can be achieved when using dynamic reconfiguration to map several sub machines onto the same hardware. This paper presents a methodology to break down the large finite state machine into many smaller machines and an architecture for the dynamically reconfiguration.
基金Supported by the National Natural Science Foundation of China(No.61834005,61772417,61802304,61602377,61874087,61634004)the Shaanxi Province Key R&D Plan(No.2021GY-029,2021KW-16).
文摘Based on the flexible quadtree partition structure of coding tree units(CTUs),the deblocking filter(DBF)in high efficiency video coding(HEVC)consumes a lot of resources when implemen-ted by hardware.It is difficult to achieve flexible switching between different sizes of coding blocks.Aiming at this problem,a reconfigurable implementation of DBF is proposed.Based on the dynamic programmable reconfigurable video array processor(DPRAP)with context switch reconfiguration mechanism,the runtime flexible switching of two coding block sizes is realized.The experimental results show that the highest work-frequency reaches 151.4 MHz.Compared with the dedicated hardware architecture scheme,the resource consumption can be reduced by 28.1%while realizing the dynamic switching between algorithms of two coding block sizes.Compared with the results of HM16.0,by using a complete I-frame for testing,the average peak signal-to-noise ratio(PSNR)of the reconfigurable implementation proposed in this paper has increased by 3.0508 dB,the coding quality has improved to a certain extent.
基金supported by the National Natural Science Foundation of China(72101270,72001213).
文摘The concept of unmanned weapon system-of-systems(UWSoS)involves a collection of various unmanned systems to achieve or accomplish a specific goal or mission.The mission reliability of UWSoS is represented by its ability to finish a required mission above the baselines of a given mission.However,issues with heterogeneity,cooperation between systems,and the emergence of UWSoS cannot be effectively solved by traditional system reliability methods.This study proposes an effective operation-loop-based mission reliability evaluation method for UWSoS by analyzing dynamic reconfiguration.First,we present a new connotation of an effective operation loop by considering the allocation of operational entities and physical resource constraints.Then,we propose an effective operationloop-based mission reliability model for a heterogeneous UWSoS according to the mission baseline.Moreover,a mission reliability evaluation algorithm is proposed under random external shocks and topology reconfiguration,revealing the evolution law of the effective operation loop and mission reliability.Finally,a typical 60-unmanned-aerial-vehicle-swarm is taken as an example to demonstrate the proposed models and methods.The mission reliability is achieved by considering external shocks,which can serve as a reference for evaluating and improving the effectiveness of UWSoS.
基金Sponsored by the National Natural Science Foundation of China(Grant Nos.61834005,61772417,61802304,61602377,and 61634004)the Shaanxi Province Coordination Innovation Project of Science and Technology(Grant No.2016KTZDGY02-04-02)+1 种基金the Shaanxi Provincial Key R&D Plan(Grant No.2017GY-060)the Shaanxi International Science and Technology Cooperation Program(Grant No.2018KW-006).
文摘The Rate Distortion Optimization(RDO)algorithm in High Efficiency Video Coding(HEVC)has many iterations and a large number of calculations.In order to decrease the calculation time and meet the requirements of fast switching of RDO algorithms of different scales,an RDO dynamic reconfigurable structure is proposed.First,the Quantization Parameter(QP)and bit rate values were loaded through an H⁃tree Configurable Network(HCN),and the execution status of the array was detected in real time.When the switching request of the RDO algorithm was detected,the corresponding configuration information was delivered.This self⁃reconfiguration implementation method improved the flexibility and utilization of hardware.Experimental results show that when the control bit width was only increased by 31.25%,the designed configuration network could increase the number of controllable processing units by 32 times,and the execution cycle was 50%lower than the same type of design.Compared with previous RDO algorithm,the RDO algorithm implemented on the reconfigurable array based on the configuration network had an average operating frequency increase of 12.5%and an area reduction of 56.4%.
基金financially supported by the National Council for Scientific and Technological Development(CNPq,Brazil),Swedish-Brazilian Research and Innovation Centre(CISB),and Saab AB under Grant No.CNPq:200053/2022-1the National Council for Scientific and Technological Development(CNPq,Brazil)under Grants No.CNPq:312924/2017-8 and No.CNPq:314660/2020-8.
文摘Unmanned aerial vehicles(UAVs)have been widely used in military,medical,wireless communications,aerial surveillance,etc.One key topic involving UAVs is pose estimation in autonomous navigation.A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system(GNSS)signal.However,some factors can interfere with the GNSS signal,such as ionospheric scintillation,jamming,or spoofing.One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images.But a high effort is required for image edge extraction.Here a support vector regression(SVR)model is proposed to reduce this computational load and processing time.The dynamic partial reconfiguration(DPR)of part of the SVR datapath is implemented to accelerate the process,reduce the area,and analyze its granularity by increasing the grain size of the reconfigurable region.Results show that the implementation in hardware is 68 times faster than that in software.This architecture with DPR also facilitates the low power consumption of 4 mW,leading to a reduction of 57%than that without DPR.This is also the lowest power consumption in current machine learning hardware implementations.Besides,the circuitry area is 41 times smaller.SVR with Gaussian kernel shows a success rate of 99.18%and minimum square error of 0.0146 for testing with the planning trajectory.This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application,thus contributing to lower power consumption,smaller hardware area,and shorter execution time.
文摘Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.
基金Project supported by the Shanghai Leading Academic Discipline Project(Grant No.J50103)the Natural Science Foundation of Jiangxi Province(Grant No.2010GZS0031)the Science Technology Project of Jiangxi Province(Grant No.2010BGB00604)
文摘As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.
基金supported by the National Natural Science Foundation of China under Grant 52077146.
文摘With the construction of the power Internet of Things(IoT),communication between smart devices in urban distribution networks has been gradually moving towards high speed,high compatibility,and low latency,which provides reliable support for reconfiguration optimization in urban distribution networks.Thus,this study proposed a deep reinforcement learning based multi-level dynamic reconfiguration method for urban distribution networks in a cloud-edge collaboration architecture to obtain a real-time optimal multi-level dynamic reconfiguration solution.First,the multi-level dynamic reconfiguration method was discussed,which included feeder-,transformer-,and substation-levels.Subsequently,the multi-agent system was combined with the cloud-edge collaboration architecture to build a deep reinforcement learning model for multi-level dynamic reconfiguration in an urban distribution network.The cloud-edge collaboration architecture can effectively support the multi-agent system to conduct“centralized training and decentralized execution”operation modes and improve the learning efficiency of the model.Thereafter,for a multi-agent system,this study adopted a combination of offline and online learning to endow the model with the ability to realize automatic optimization and updation of the strategy.In the offline learning phase,a Q-learning-based multi-agent conservative Q-learning(MACQL)algorithm was proposed to stabilize the learning results and reduce the risk of the next online learning phase.In the online learning phase,a multi-agent deep deterministic policy gradient(MADDPG)algorithm based on policy gradients was proposed to explore the action space and update the experience pool.Finally,the effectiveness of the proposed method was verified through a simulation analysis of a real-world 445-node system.
基金Science and Technology Development Fund of Tianjin s Universities(20070813)
文摘Presented is a global dynamic reconfiguration design of an artificial neural network based on field programmable gate array(FPGA). Discussed are the dynamic reconfiguration principles and methods. Proposed is a global dynamic reconfiguration scheme using Xilinx FPGA and platform flash. Using the revision capabilities of Xilinx XCF32P platform flash, an artificial neural network based on Xilinx XC2V30P Virtex-Ⅱ can be reconfigured dynamically from back propagation(BP) learning algorithms to BP network testing algorithms. The experimental results indicate that the scheme is feasible, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably.
基金Science and Technology Innovation Fund of Tianjin(06FZZDGX01800)
文摘The dynamic reconfiguration technique based on field-programmable gate array （FPGA） can improve the resource utilization. Discussed are the dynamic reconfiguration principles and methods. Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-Ⅱ FPGA and SMCS Ethernet Physical layer transceiver（PHY）. The hardware of the system is designed with Xilinx Virtex-U XC2V30P FPGA that embedds MicroBlaze and MAC IP core, and its network communication software based on transmission control protoeol/Internet protocol （TCP/IP） protocol is programmed by loading LwIP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system（RFDRS） can switch freely in the eight lighting modes of light emitting diodes （LED）, and that, using dynamic reconfiguration technology, FPGA resource utilization can be reduced remarkably, which is advantageous in the system upgrade and software update.
基金supported in part by the European Regional Development Fund under Grant KK.01.1.1.01.0009(DATACROSS).
文摘This paper deals with reduction of losses in electric power distribution system through a dynamic reconfiguration case study of a grid in the city of Mostar,Bosnia and Herzegovina.The proposed solution is based on a nonlinear model predictive control algorithm which determines the optimal switching operations of the distribution system.The goal of the control algorithm is to find the optimal radial network topology which minimizes cumulative active power losses and maximizes voltages across the network while simultaneously satisfying all system constraints.The optimization results are validated through multiple simulations(using real power demand data collected for a few characteristic days during winter and summer)which demonstrate the efficiency and usefulness of the developed control algorithm in reducing the grid losses by up to 14%.
基金Foundation item： the National Natural Science Foundation of China （No. 61136002）, the Key Project of Chinese Ministry of Education （No. 211180）, and the Shaanxi Provincial Industrial and Technological Project （No. 2011k06-47）.
文摘This paper describes a dynamically reconfigurable data-flow hardware architecture optimized for the computation of image and video. It is a scalable hierarchically organized parallel architecture that consists of data-flow clusters and finite-state machine （FSM） controllers. Each cluster contains various kinds of ceils that are optimized for video processing. Furthermore, to facilitate the design process, we provide a C-like language for design specification and associated design tools. Some video applications have been implemented in the architecture to demonstrate the applicability and flexibility of the architecture. Experimental results show that the architecture, along with its video applications, can be used in many real-time video processing.
基金supported by the National Natural Science Foundation of China under Grant U21A20462.
文摘This paper introduces a novel RISC-V processor architecture designed for ultra-low-power and energy-efficient applications,particularly for Internet of things(IoT)devices.The architecture enables runtime dynamic reconfiguration of the datapath,allowing efficient balancing between computational performance and power consumption.This is achieved through interchangeable components and clock gating mechanisms,which help the processor adapt to varying workloads.A prototype of the architecture was implemented on a Xilinx Artix 7 field programmable gate array(FPGA).Experimental results show significant improvements in power efficiency and performance.The mini configuration achieves an impressive reduction in power consumption,using only 36%of the baseline power.Meanwhile,the full configuration boosts performance by 8%over the baseline.The flexible and adaptable nature of this architecture makes it highly suitable for a wide range of low-power IoT applications,providing an effective solution to meet the growing demands for energy efficiency in modern IoT devices.
基金National Natural Science Foundation of China(Nos.12275065 and 12275064)Natural Science Foundation of Hebei Province(No.A2021201010)+3 种基金Interdisciplinary Research Program of Natural Science of Hebei University(No.DXK202108)Hebei Provincial Central Government Guiding Local Science and Technology Development Funds(No.236Z1501G)Scientific Research and Innovation Team Foundation of Hebei University(No.IT2023B03)The Excellent Youth Research Innovation Team of Hebei University(QNTD202402).
文摘Continuous development of photonic crystals(PCs)over the last 30 years has carved out many new scientific frontiers.However,creating tunable PCs that enable flexible control of geometric configurations remains a challenge.Here we present a scheme to produce a tunable plasma photonic crystal(PPC)‘kaleidoscope’with rich diversity of structural configurations in dielectric barrier discharge.Multi-freedom control of the PPCs,including the symmetry,dielectric constant,crystal orientation,lattice constant,topological state,and structures of scattering elements,has been realized.Four types of lattice reconfigurations are demonstrated,including transitions from periodic to periodic,disordered to ordered,non-topological to topological,and striped to honeycomb Moirélattices.Furthermore,alterations in photonic band structures corresponding to the reconstruction of various PPCs have been investigated.Our system presents a promising platform for generating a PPC‘kaleidoscope’,offering benefits such as reduced equipment requirements,low cost,rapid response,and enhanced flexibility.This development opens up new opportunities for both fundamental and applied research.
基金National Natural Science Foundation of China （90505013）
文摘As aerospace vehicles travel in a hellish environment, the reliability of the measuring and controlling systems has played a critical role in the credibility of a whole airborne system. Embryo-electronic system is a bionic hardware capable of self-diagnosing and self-healing. This article presents a new approach to design embryo-electronic systems and introduces their bionic principles, system structures and fanlt-tolerant mechanism. As the current methods cannot meet the requirements for large-scale embryo-electronic systems, this article advances a new shift-register-based configuration memory of embryonic system to solve the problem by using the inter-cell communication to reduce the gene storage capacity of a single cell. The article designs an overall structure of the shift-register-based configuration memories of the embryonic system and connects them into a chain structure. The article also designs an inner circuit of the cell, the control of shift-register-based configuration memory and the way of runtime dynamic configuration. The simulation of field programmable gate array （FPGA） evidences the realizability of the proposed design. Compared to the SRAM-based one, this memory can save 90% of the area when constructing embryonic systems larger than 128× 128 under the same condition.
基金supported by the National Key R&D Program of China (No.2019YFE0123600)National Natural Science Foundation of China (No.52077146)Young Elite Scientists Sponsorship Program by CSEE (No.CESS-YESS-2019027)。
文摘The increasing integration of photovoltaic generators(PVGs) and the uneven economic development in different regions may cause the unbalanced spatial-temporal distribution of load demands in an urban distribution network(UDN). This may lead to undesired consequences, including PVG curtailment, load shedding, and equipment inefficiency, etc. Global dynamic reconfiguration provides a promising method to solve those challenges. However, the power flow transfer capabilities for different kinds of switches are diverse, and the willingness of distribution system operators(DSOs) to select them is also different. In this paper, we formulate a multi-objective dynamic reconfiguration optimization model suitable for multi-level switching modes to minimize the operation cost, load imbalance, and the PVG curtailment. The multi-level switching includes feeder-level switching, transformer-level switching, and substation-level switching. A novel load balancing index is devised to quantify the global load balancing degree at different levels. Then, a stochastic programming model based on selected scenarios is established to address the uncertainties of PVGs and loads. Afterward, the fuzzy c-means(FCMs) clustering is applied to divide the time periods of reconfiguration. Furthermore, the modified binary particle swarm optimization(BPSO)and Cplex solver are combined to solve the proposed mixed-integer second-order cone programming(MISOCP) model. Numerical results based on the 148-node and 297-node systems are obtained to validate the effectiveness of the proposed method.
