Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless com...Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.展开更多
The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this...The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this paper investigates the energy efficiency(EE)maximization problem for downlink cooperative non-orthogonal multiple access(C-NOMA)systems with hardware impairments(HIs).The base station(BS)communicates with several users via a half-duplex(HD)amplified-and-forward(AF)relay.First,we formulate the EE maximization problem of the system under HIs by jointly optimizing transmit power and power allocated coefficient(PAC)at BS,and transmit power at the relay.The original EE maximization problem is a non-convex problem,which is challenging to give the optimal solution directly.First,we use fractional programming to convert the EE maximization problem as a series of subtraction form subproblems.Then,variable substitution and block coordinate descent(BCD)method are used to handle the sub-problems.Next,a resource allocation algorithm is proposed to maximize the EE of the systems.Finally,simulation results show that the proposed algorithm outperforms the downlink cooperative orthogonal multiple access(C-OMA)scheme.展开更多
Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro...Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro-posed to improve the efficiency for edge inference of Deep Neural Networks(DNNs),existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead,and their efficiency is bounded by the bottleneck of computation latency and memory footprint.To tackle this challenge,we present an efficient inference approach on the basis of PoT quantization and model compression.An integer-only scalar PoT quantization(IOS-PoT)is designed jointly with a distribution loss regularizer,wherein the regularizer minimizes quantization errors and training disturbances.Additionally,two-stage model compression is developed to effectively reduce memory requirement,and alleviate bandwidth usage in communications of networked heterogenous learning systems.The product look-up table(P-LUT)inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators.Finally,comprehensive experiments on Residual Networks(ResNets)and efficient architectures with Canadian Institute for Advanced Research(CIFAR),ImageNet,and Real-world Affective Faces Database(RAF-DB)datasets,indicate that our approach achieves 2×∼10×improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods.A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array(FPGA)platform for accelerating convolution operations,with performance results showing that P-LUT reduces memory footprint by 1.45×,achieves more than 3×power efficiency and 2×resource efficiency,compared to the conventional bit-shifting scheme.展开更多
The Internet of Vehicles(IoV)will carry a large amount of security and privacy-related data,which makes the secure communication between the IoV terminals increasingly critical.This paper studies the joint beamforming...The Internet of Vehicles(IoV)will carry a large amount of security and privacy-related data,which makes the secure communication between the IoV terminals increasingly critical.This paper studies the joint beamforming for physical-layer security transmission in the coexistence of Vehicle-to-Infrastructure(V2I)and Vehicle-toVehicle(V2V)communication with Reconfigurable Intelligent Surface(RIS)assistance,taking into account hardware impairments.A communication model for physical-layer security transmission is established when the eavesdropping user is present and the base station antenna has hardware impairments assisted by RIS.Based on this model,we propose to maximize the V2I physical-layer security transmission rate.To solve the coupled non-convex optimization problem,an alternating optimization algorithm based on second-order cone programming and semidefinite relaxation is proposed to obtain the optimal V2I base station transmit precoding and RIS reflect phase shift matrix.Finally,simulation results are presented to verify the convergence and superiority of our proposed algorithm while analyzing the impact of system parameters on the V2I physical-layer security transmission rate.The simulation results further demonstrate that the proposed robust beamforming algorithm considering hardware impairments will achieve an average performance improvement of 0.7 dB over a non-robustly designed algorithm.Furthermore,increasing the number of RIS reflective units from 10 to 50 results in an almost 2 dB enhancement in secure transmission rate.展开更多
The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization...The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.展开更多
As friction, intrinsic steady-state nonlinearity poses a challenging dilemma to the control system of 3-DOF （three degree of freedom） flight simulator, a novel hybrid control strategy of nonlinear PID （proportional...As friction, intrinsic steady-state nonlinearity poses a challenging dilemma to the control system of 3-DOF （three degree of freedom） flight simulator, a novel hybrid control strategy of nonlinear PID （proportionalintegral-derivative） with additional FFC （feed-forward controller） is proposed, and the hardware-in-the-loop simulation results are also given. Based on the description of 3-DOF flight simulator, a novel nonlinear PID theory is well introduced. Then a nonlinear PID controller with additional FFC is designed. Subsequently, the loop structure of 3-DOF flight simulator is also designed. Finally, a series of hardware-in-the-loop simulation experiments are undertaken to verify the feasibility and effectiveness of the proposed nonlinear PID controller with additional FFC for 3-DOF flight simulator.展开更多
A ground-based hardware-in-the-loop （HIL） simulation system with hydraulically driven Stewart platform for spacecraft docking simulation is presented. The system is used for simulating docking process of the on-orbi...A ground-based hardware-in-the-loop （HIL） simulation system with hydraulically driven Stewart platform for spacecraft docking simulation is presented. The system is used for simulating docking process of the on-orbit spacecraft. Principle and structure of the six-degree-of-freedom simulation system are introduced. The docking process dynamic of the vehicles is modeled. Experiment results and mathematical simulation data are compared to validating the simulation system. The comparisons of the results prove that the simulation system proposed can effectively simulate the on-orbit docking process of the spacecraft.展开更多
Nowadays validation of anti-lock braking systems（ABS） relies mainly on a large amount of road tests.An alternative means with higher efficiency is employing the hardware-in-the-loop simulation（HILS） system to subs...Nowadays validation of anti-lock braking systems（ABS） relies mainly on a large amount of road tests.An alternative means with higher efficiency is employing the hardware-in-the-loop simulation（HILS） system to substitute part of road tests for designing,testing,and tuning electronic control units（ECUs） of ABS.Most HILS systems for ABS use expensive digital signal processor hardware and special purpose software,and some fail-safe functions with regard to wheel speeds cannot be evaluated since artificial wheel speed signals are usually provided.In this paper,a low-cost ABS HILS test bench is developed and used for validating the anti-lock braking performance and tuning control parameters of ABS controllers.Another important merit of the proposed test bench is that it can comprehensively evaluate the fail-safe functions with regard to wheel speed signals since real tone rings and sensors are integrated in the bench.A 5-DOF vehicle model with consideration of longitudinal load transfer is used to calculate tire forces,wheel speeds and vehicle speed.Each of the four real-time wheel speed signal generators consists of a servo motor plus a ring gear,which has sufficient dynamic response ability to emulate the rapid changes of the wheel speeds under strict braking conditions of very slippery roads.The simulation of braking tests under different road adhesion coefficients using the HILS test bench is run,and results show that it can evaluate the anti-lock braking performance of ABS and partly the fail-safe functions.This HILS system can also be used in such applications as durability test,benchmarking and comparison between different ECUs.The test bench developed not only has a relatively low cost,but also can be used to validate the wheel speed-related ECU design and all its fail-safe functions,and a rapid testing and proving platform with a high efficiency for research and development of the automotive ABS is therefore provided.展开更多
A typical electronic communication system, such as GPS receiver, unmanned aerial vehicle＇s （UAV＇s） data link, and radar, faces multi-dimensional and complicated electromagnetic interference in operating environmen...A typical electronic communication system, such as GPS receiver, unmanned aerial vehicle＇s （UAV＇s） data link, and radar, faces multi-dimensional and complicated electromagnetic interference in operating environment. To measure the anti- interference performance of the electronic communication system in the complicated electromagnetic interference environment, a method of multi-dimensional and complicated electromagnetic interference hardware-in-the-loop simulation in an anechoic room is proposed. It takes into account the characteristics of interference signals and the positional relationship among interference, the receiver and the transmitter of the electronic communication system. It uses the grey relational method and the angular domain mapping error correction method to control the relevant parameters, the microwave switch and so on, thus achieving the approximately actual mapping of the outdoor multi-dimensional and complicated electromagnetic interference in the anechoic room. To verify the effectiveness of this method, the multi-dimensional and complicated electromagnetic interference of the UAV＇s data link is simulated as an example. The results show that the degree of correlation between the calculated signal to interference ratio of the data link receiver in the actual scene and the measured signal to interference ratio of the data link receiver simulated with this method in the anechoic room is 0.968 1, proving that the method is effective for simulating the complicated electromagnetic interference.展开更多
A hardware-in-the-loop simulating platform is developed to avoid designing defects caused by the complicated logical structure and multiple-functional buildup of the dectronic control unit（ECU）in modem diesel engine...A hardware-in-the-loop simulating platform is developed to avoid designing defects caused by the complicated logical structure and multiple-functional buildup of the dectronic control unit（ECU）in modem diesel engines, and to diminish potential damages on components or human exposure to dangers in R＆D en- deavor. This plat-form consists of a computer installed with software Matlab/Simulink/RTW and dSPACE/ ControlDesk; a diesel engine ECU, and a dSPACE autobox which runs a real-time diesel engine model. A typical model of diesel engine with turbocharger and intercooler is presented. Based on this model our research is carried out with a real ECU to test its software control strategies. Results show that by using the diesel engine model downloaded inside, the hardware-in-the-loop platform can simulate diesel engine＇s working conditions and generate all kinds of sensor signals which ECU needs on a real-time basis. So the ECU control strategies can be validated and relevant parameters roughly calibrated.展开更多
To enhance the fidelity and accuracy of the simulation of communication networks,hardware-in-the-loop（HITL） simulation was employed.HITL simulation methods was classified into three categories,of which the merits an...To enhance the fidelity and accuracy of the simulation of communication networks,hardware-in-the-loop（HITL） simulation was employed.HITL simulation methods was classified into three categories,of which the merits and shortages were compared.Combing system-in-the-loop（SITL） simulation principle with high level architecture（HLA）,an HITL simulation model of asynchronous transfer mode（ATM） network was constructed.The throughput and end-to-end delay of all-digital simulation and HITL simulation was analyzed,which showed that HITL simulation was more reliable and effectively improved the simulation credibility of communication network.Meanwhile,HLA-SITL method was fast and easy to achieve and low-cost during design lifecycle.Thus,it was a feasible way to research and analyze the large-scale network.展开更多
In the large-scale distributed hardware-in-the-loop radar simulation system based on HLA, a new solution of processing after acquisition is proposed, which separates the software subsystem from the hardware jammer sub...In the large-scale distributed hardware-in-the-loop radar simulation system based on HLA, a new solution of processing after acquisition is proposed, which separates the software subsystem from the hardware jammer subsystem by a response database, so as to settle the problem, that the software subsystem can not meet the real-time need of the hardware, with very little increment of code. And the data completeness and feasibility of this solution are discussed.展开更多
In the proposed paper, the new experimental results are described obtained from the laboratory stand and the model developed by the authors. A method of acquiring characteristics of a pump motor drive using a hardware...In the proposed paper, the new experimental results are described obtained from the laboratory stand and the model developed by the authors. A method of acquiring characteristics of a pump motor drive using a hardware-in-the-loop simulation approach is explained. To explore the centrifugal pumps manufactured by ABB, their own control system is used whereas an industrial pump is replaced with the specially designed simulator. To clarify the model topology and parameters, a double-machine assembly was designed and used as universal pump prototype. A library of reference and disturbance signals used in pumping was applied as a modeling tool. In this way, the advantages of mathematical and physical simulations have been combined with optimal interaction of both approaches.展开更多
A hardwale demodulation method for 2-D edge detection is proposed. The filtering step and the differential step are implemented by using the hardware circuit. This demodulation circuit simplifies the edgefinder and re...A hardwale demodulation method for 2-D edge detection is proposed. The filtering step and the differential step are implemented by using the hardware circuit. This demodulation circuit simplifies the edgefinder and reduces the measuring cycle. The calibration method of scale setting is also presented,and bymeasuring some calibrated objects,the demodulation errors and the error correction table is obtained.展开更多
The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system st...The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export design, and discusses the network hardware system design and optimization for different scale universities according to different practical demand. The objective is that the network hardware system can meet the demand and have been made full use.展开更多
The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative...The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging.展开更多
Scientific research requires the collection of data in order to study, monitor, analyze, describe, or understand a particular process or event. Data collection efforts are often a compromise: manual measurements can b...Scientific research requires the collection of data in order to study, monitor, analyze, describe, or understand a particular process or event. Data collection efforts are often a compromise: manual measurements can be time-consuming and labor-intensive, resulting in data being collected at a low frequency, while automating the data-collection process can reduce labor requirements and increase the frequency of measurements, but at the cost of added expense of electronic data-collecting instrumentation. Rapid advances in electronic technologies have resulted in a variety of new and inexpensive sensing, monitoring, and control capabilities which offer opportunities for implementation in agricultural and natural-resource research applications. An Open Source Hardware project called Arduino consists of a programmable microcontroller development platform, expansion capability through add-on boards, and a programming development environment for creating custom microcontroller software. All circuit-board and electronic component specifications, as well as the programming software, are open-source and freely available for anyone to use or modify. Inexpensive sensors and the Arduino development platform were used to develop several inexpensive, automated sensing and datalogging systems for use in agricultural and natural-resources related research projects. Systems were developed and implemented to monitor soil-moisture status of field crops for irrigation scheduling and crop-water use studies, to measure daily evaporation-pan water levels for quantifying evaporative demand, and to monitor environmental parameters under forested conditions. These studies demonstrate the usefulness of automated measurements, and offer guidance for other researchers in developing inexpensive sensing and monitoring systems to further their research.展开更多
Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge,...Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge, this paper proposes a framework, called HooklMA, to detect compromised kernel hooks by using hardware debugging features. The key contribution of the work is that context information is captured from hardware instead of from relatively vulnerable kernel data. Using commodity hardware, a proof-of-concept pro- totype system of HooklMA has been developed. This prototype handles 3 082 dynamic control-flow transfers with related hooks in the kernel space. Experiments show that HooklMA is capable of detecting compomised kernel hooks caused by kernel rootkits. Performance evaluations with UnixBench indicate that runtirre overhead introduced by HooklMA is about 21.5%.展开更多
Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficu...Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficult to detecte due to its minimal resource occupation. In order to achieve an accurate detection with high efficiency, a HT detection method based on the electromagnetic leakage of the chip is proposed in this paper. At first, the dimensionality reduction and the feature extraction of the electromagnetic leakage signals in each group(template chip, Trojan-free chip and target chip) were realized by principal component analysis(PCA). Then, the Mahalanobis distances between the template group and the other groups were calculated. Finally, the differences between the Mahalanobis distances and the threshold were compared to determine whether the HT had been implanted into the target chip. In addition, the concept of the HT Detection Quality(HTDQ) was proposed to analyze and compare the performance of different detection methods. Our experiment results indicate that the accuracy of this detection method is 91.93%, and the time consumption is 0.042s in average, which shows a high HTDQ compared with three other methods.展开更多
Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full...Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.展开更多
基金supported in part by the Sichuan Science and Technology Program(Grant No.2023YFG0316)the Industry-University Research Innovation Fund of China University(Grant No.2021ITA10016)+1 种基金the Key Scientific Research Fund of Xihua University(Grant No.Z1320929)the Special Funds of Industry Development of Sichuan Province(Grant No.zyf-2018-056).
文摘Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.
基金partially supported by the National Natural Science Foundation of China under Grant 61701064Chongqing Natural Science Foundation under Grant cstc2019jcyj-msxmX0264Sichuan Science and Technology Program under Grant 2022YFQ0017。
文摘The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this paper investigates the energy efficiency(EE)maximization problem for downlink cooperative non-orthogonal multiple access(C-NOMA)systems with hardware impairments(HIs).The base station(BS)communicates with several users via a half-duplex(HD)amplified-and-forward(AF)relay.First,we formulate the EE maximization problem of the system under HIs by jointly optimizing transmit power and power allocated coefficient(PAC)at BS,and transmit power at the relay.The original EE maximization problem is a non-convex problem,which is challenging to give the optimal solution directly.First,we use fractional programming to convert the EE maximization problem as a series of subtraction form subproblems.Then,variable substitution and block coordinate descent(BCD)method are used to handle the sub-problems.Next,a resource allocation algorithm is proposed to maximize the EE of the systems.Finally,simulation results show that the proposed algorithm outperforms the downlink cooperative orthogonal multiple access(C-OMA)scheme.
基金This work was supported by Open Fund Project of State Key Laboratory of Intelligent Vehicle Safety Technology by Grant with No.IVSTSKL-202311Key Projects of Science and Technology Research Programme of Chongqing Municipal Education Commission by Grant with No.KJZD-K202301505+1 种基金Cooperation Project between Chongqing Municipal Undergraduate Universities and Institutes Affiliated to the Chinese Academy of Sciences in 2021 by Grant with No.HZ2021015Chongqing Graduate Student Research Innovation Program by Grant with No.CYS240801.
文摘Massive computational complexity and memory requirement of artificial intelligence models impede their deploy-ability on edge computing devices of the Internet of Things(IoT).While Power-of-Two(PoT)quantization is pro-posed to improve the efficiency for edge inference of Deep Neural Networks(DNNs),existing PoT schemes require a huge amount of bit-wise manipulation and have large memory overhead,and their efficiency is bounded by the bottleneck of computation latency and memory footprint.To tackle this challenge,we present an efficient inference approach on the basis of PoT quantization and model compression.An integer-only scalar PoT quantization(IOS-PoT)is designed jointly with a distribution loss regularizer,wherein the regularizer minimizes quantization errors and training disturbances.Additionally,two-stage model compression is developed to effectively reduce memory requirement,and alleviate bandwidth usage in communications of networked heterogenous learning systems.The product look-up table(P-LUT)inference scheme is leveraged to replace bit-shifting with only indexing and addition operations for achieving low-latency computation and implementing efficient edge accelerators.Finally,comprehensive experiments on Residual Networks(ResNets)and efficient architectures with Canadian Institute for Advanced Research(CIFAR),ImageNet,and Real-world Affective Faces Database(RAF-DB)datasets,indicate that our approach achieves 2×∼10×improvement in the reduction of both weight size and computation cost in comparison to state-of-the-art methods.A P-LUT accelerator prototype is implemented on the Xilinx KV260 Field Programmable Gate Array(FPGA)platform for accelerating convolution operations,with performance results showing that P-LUT reduces memory footprint by 1.45×,achieves more than 3×power efficiency and 2×resource efficiency,compared to the conventional bit-shifting scheme.
基金the Key Research and Development Plan of Jiangsu Province,grant number BE2020084-2the National Key Research and Development Program of China,grant number 2020YFB1600104.
文摘The Internet of Vehicles(IoV)will carry a large amount of security and privacy-related data,which makes the secure communication between the IoV terminals increasingly critical.This paper studies the joint beamforming for physical-layer security transmission in the coexistence of Vehicle-to-Infrastructure(V2I)and Vehicle-toVehicle(V2V)communication with Reconfigurable Intelligent Surface(RIS)assistance,taking into account hardware impairments.A communication model for physical-layer security transmission is established when the eavesdropping user is present and the base station antenna has hardware impairments assisted by RIS.Based on this model,we propose to maximize the V2I physical-layer security transmission rate.To solve the coupled non-convex optimization problem,an alternating optimization algorithm based on second-order cone programming and semidefinite relaxation is proposed to obtain the optimal V2I base station transmit precoding and RIS reflect phase shift matrix.Finally,simulation results are presented to verify the convergence and superiority of our proposed algorithm while analyzing the impact of system parameters on the V2I physical-layer security transmission rate.The simulation results further demonstrate that the proposed robust beamforming algorithm considering hardware impairments will achieve an average performance improvement of 0.7 dB over a non-robustly designed algorithm.Furthermore,increasing the number of RIS reflective units from 10 to 50 results in an almost 2 dB enhancement in secure transmission rate.
文摘The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs.
基金the National Natural Science Foundation of China (60604009)Aeronautical Science Foundationof China(2006ZC51039)Beijing NOVA Program (2007A017).
文摘As friction, intrinsic steady-state nonlinearity poses a challenging dilemma to the control system of 3-DOF （three degree of freedom） flight simulator, a novel hybrid control strategy of nonlinear PID （proportionalintegral-derivative） with additional FFC （feed-forward controller） is proposed, and the hardware-in-the-loop simulation results are also given. Based on the description of 3-DOF flight simulator, a novel nonlinear PID theory is well introduced. Then a nonlinear PID controller with additional FFC is designed. Subsequently, the loop structure of 3-DOF flight simulator is also designed. Finally, a series of hardware-in-the-loop simulation experiments are undertaken to verify the feasibility and effectiveness of the proposed nonlinear PID controller with additional FFC for 3-DOF flight simulator.
文摘A ground-based hardware-in-the-loop （HIL） simulation system with hydraulically driven Stewart platform for spacecraft docking simulation is presented. The system is used for simulating docking process of the on-orbit spacecraft. Principle and structure of the six-degree-of-freedom simulation system are introduced. The docking process dynamic of the vehicles is modeled. Experiment results and mathematical simulation data are compared to validating the simulation system. The comparisons of the results prove that the simulation system proposed can effectively simulate the on-orbit docking process of the spacecraft.
基金supported by National Natural Science Foundation of China(Grant No.50908008)National Hi-tech Research and Development Program of China(863Program,Grant No.2009AA11Z216)
文摘Nowadays validation of anti-lock braking systems（ABS） relies mainly on a large amount of road tests.An alternative means with higher efficiency is employing the hardware-in-the-loop simulation（HILS） system to substitute part of road tests for designing,testing,and tuning electronic control units（ECUs） of ABS.Most HILS systems for ABS use expensive digital signal processor hardware and special purpose software,and some fail-safe functions with regard to wheel speeds cannot be evaluated since artificial wheel speed signals are usually provided.In this paper,a low-cost ABS HILS test bench is developed and used for validating the anti-lock braking performance and tuning control parameters of ABS controllers.Another important merit of the proposed test bench is that it can comprehensively evaluate the fail-safe functions with regard to wheel speed signals since real tone rings and sensors are integrated in the bench.A 5-DOF vehicle model with consideration of longitudinal load transfer is used to calculate tire forces,wheel speeds and vehicle speed.Each of the four real-time wheel speed signal generators consists of a servo motor plus a ring gear,which has sufficient dynamic response ability to emulate the rapid changes of the wheel speeds under strict braking conditions of very slippery roads.The simulation of braking tests under different road adhesion coefficients using the HILS test bench is run,and results show that it can evaluate the anti-lock braking performance of ABS and partly the fail-safe functions.This HILS system can also be used in such applications as durability test,benchmarking and comparison between different ECUs.The test bench developed not only has a relatively low cost,but also can be used to validate the wheel speed-related ECU design and all its fail-safe functions,and a rapid testing and proving platform with a high efficiency for research and development of the automotive ABS is therefore provided.
基金supported by the National Natural Science Foundation of China(61571368)the certain Ministry Foundation(2014607B006)
文摘A typical electronic communication system, such as GPS receiver, unmanned aerial vehicle＇s （UAV＇s） data link, and radar, faces multi-dimensional and complicated electromagnetic interference in operating environment. To measure the anti- interference performance of the electronic communication system in the complicated electromagnetic interference environment, a method of multi-dimensional and complicated electromagnetic interference hardware-in-the-loop simulation in an anechoic room is proposed. It takes into account the characteristics of interference signals and the positional relationship among interference, the receiver and the transmitter of the electronic communication system. It uses the grey relational method and the angular domain mapping error correction method to control the relevant parameters, the microwave switch and so on, thus achieving the approximately actual mapping of the outdoor multi-dimensional and complicated electromagnetic interference in the anechoic room. To verify the effectiveness of this method, the multi-dimensional and complicated electromagnetic interference of the UAV＇s data link is simulated as an example. The results show that the degree of correlation between the calculated signal to interference ratio of the data link receiver in the actual scene and the measured signal to interference ratio of the data link receiver simulated with this method in the anechoic room is 0.968 1, proving that the method is effective for simulating the complicated electromagnetic interference.
基金Sponsored by the Ministerial Level Advanced Research(10660060220)
文摘A hardware-in-the-loop simulating platform is developed to avoid designing defects caused by the complicated logical structure and multiple-functional buildup of the dectronic control unit（ECU）in modem diesel engines, and to diminish potential damages on components or human exposure to dangers in R＆D en- deavor. This plat-form consists of a computer installed with software Matlab/Simulink/RTW and dSPACE/ ControlDesk; a diesel engine ECU, and a dSPACE autobox which runs a real-time diesel engine model. A typical model of diesel engine with turbocharger and intercooler is presented. Based on this model our research is carried out with a real ECU to test its software control strategies. Results show that by using the diesel engine model downloaded inside, the hardware-in-the-loop platform can simulate diesel engine＇s working conditions and generate all kinds of sensor signals which ECU needs on a real-time basis. So the ECU control strategies can be validated and relevant parameters roughly calibrated.
基金Supported by the National Natural Science Foundation of China (61101129)Specialized Research Fund for the Doctoral Program of Higher Education(20091101110019)
文摘To enhance the fidelity and accuracy of the simulation of communication networks,hardware-in-the-loop（HITL） simulation was employed.HITL simulation methods was classified into three categories,of which the merits and shortages were compared.Combing system-in-the-loop（SITL） simulation principle with high level architecture（HLA）,an HITL simulation model of asynchronous transfer mode（ATM） network was constructed.The throughput and end-to-end delay of all-digital simulation and HITL simulation was analyzed,which showed that HITL simulation was more reliable and effectively improved the simulation credibility of communication network.Meanwhile,HLA-SITL method was fast and easy to achieve and low-cost during design lifecycle.Thus,it was a feasible way to research and analyze the large-scale network.
基金the Ministerial Level Advanced Research Foundation
文摘In the large-scale distributed hardware-in-the-loop radar simulation system based on HLA, a new solution of processing after acquisition is proposed, which separates the software subsystem from the hardware jammer subsystem by a response database, so as to settle the problem, that the software subsystem can not meet the real-time need of the hardware, with very little increment of code. And the data completeness and feasibility of this solution are discussed.
文摘In the proposed paper, the new experimental results are described obtained from the laboratory stand and the model developed by the authors. A method of acquiring characteristics of a pump motor drive using a hardware-in-the-loop simulation approach is explained. To explore the centrifugal pumps manufactured by ABB, their own control system is used whereas an industrial pump is replaced with the specially designed simulator. To clarify the model topology and parameters, a double-machine assembly was designed and used as universal pump prototype. A library of reference and disturbance signals used in pumping was applied as a modeling tool. In this way, the advantages of mathematical and physical simulations have been combined with optimal interaction of both approaches.
文摘A hardwale demodulation method for 2-D edge detection is proposed. The filtering step and the differential step are implemented by using the hardware circuit. This demodulation circuit simplifies the edgefinder and reduces the measuring cycle. The calibration method of scale setting is also presented,and bymeasuring some calibrated objects,the demodulation errors and the error correction table is obtained.
文摘The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export design, and discusses the network hardware system design and optimization for different scale universities according to different practical demand. The objective is that the network hardware system can meet the demand and have been made full use.
文摘The interpretation of spinal images fixed with metallic hardware forms an increasing bulk of daily practice in a busy imaging department. Radiologists are required to be familiar with the instrumentation and operative options used in spinal fixation and fusion procedures, especially in his or her institute. This is critical in evaluating the position of implants and potential complications associated with the operative approaches and spinal fixation devices used. Thus, the radiologist can play an important role in patient care and outcome. This review outlines the advantages and disadvantages of commonly used imaging methods and reports on the best yield for each modality and how to overcome the problematic issues associated with the presence of metallic hardware during imaging. Baseline radiographs are essential as they are the baseline point for evaluation of future studies should patients develop symptoms suggesting possible complications. They may justify further imaging workup with computed tomography, magnetic resonance and/or nuclear medicine studies as the evaluation of a patient with a spinal implant involves a multi-modality approach. This review describes imaging features of potential complications associated with spinal fusion surgery as well as the instrumentation used. This basic knowledge aims to help radiologists approach everyday practice in clinical imaging.
文摘Scientific research requires the collection of data in order to study, monitor, analyze, describe, or understand a particular process or event. Data collection efforts are often a compromise: manual measurements can be time-consuming and labor-intensive, resulting in data being collected at a low frequency, while automating the data-collection process can reduce labor requirements and increase the frequency of measurements, but at the cost of added expense of electronic data-collecting instrumentation. Rapid advances in electronic technologies have resulted in a variety of new and inexpensive sensing, monitoring, and control capabilities which offer opportunities for implementation in agricultural and natural-resource research applications. An Open Source Hardware project called Arduino consists of a programmable microcontroller development platform, expansion capability through add-on boards, and a programming development environment for creating custom microcontroller software. All circuit-board and electronic component specifications, as well as the programming software, are open-source and freely available for anyone to use or modify. Inexpensive sensors and the Arduino development platform were used to develop several inexpensive, automated sensing and datalogging systems for use in agricultural and natural-resources related research projects. Systems were developed and implemented to monitor soil-moisture status of field crops for irrigation scheduling and crop-water use studies, to measure daily evaporation-pan water levels for quantifying evaporative demand, and to monitor environmental parameters under forested conditions. These studies demonstrate the usefulness of automated measurements, and offer guidance for other researchers in developing inexpensive sensing and monitoring systems to further their research.
基金The authors would like to thank the anonymous reviewers for their insightful corrnlents that have helped improve the presentation of this paper. The work was supported partially by the National Natural Science Foundation of China under Grants No. 61070192, No.91018008, No. 61170240 the National High-Tech Research Development Program of China under Grant No. 2007AA01ZA14 the Natural Science Foundation of Beijing un- der Grant No. 4122041.
文摘Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge, this paper proposes a framework, called HooklMA, to detect compromised kernel hooks by using hardware debugging features. The key contribution of the work is that context information is captured from hardware instead of from relatively vulnerable kernel data. Using commodity hardware, a proof-of-concept pro- totype system of HooklMA has been developed. This prototype handles 3 082 dynamic control-flow transfers with related hooks in the kernel space. Experiments show that HooklMA is capable of detecting compomised kernel hooks caused by kernel rootkits. Performance evaluations with UnixBench indicate that runtirre overhead introduced by HooklMA is about 21.5%.
基金supported by the Special Funds for Basic Scientific Research Business Expenses of Central Universities No. 2014GCYY0the Beijing Natural Science Foundation No. 4163076the Fundamental Research Funds for the Central Universities No. 328201801
文摘Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficult to detecte due to its minimal resource occupation. In order to achieve an accurate detection with high efficiency, a HT detection method based on the electromagnetic leakage of the chip is proposed in this paper. At first, the dimensionality reduction and the feature extraction of the electromagnetic leakage signals in each group(template chip, Trojan-free chip and target chip) were realized by principal component analysis(PCA). Then, the Mahalanobis distances between the template group and the other groups were calculated. Finally, the differences between the Mahalanobis distances and the threshold were compared to determine whether the HT had been implanted into the target chip. In addition, the concept of the HT Detection Quality(HTDQ) was proposed to analyze and compare the performance of different detection methods. Our experiment results indicate that the accuracy of this detection method is 91.93%, and the time consumption is 0.042s in average, which shows a high HTDQ compared with three other methods.
文摘Ethernet over SDH/SONET (EOS) is a hotspot in today's data transmission technology for it combines the merits of both Ethernet and SDH/SONET. However, implementing an EOS system on a chip is complex and needs full verifications. This paper introduces our design of Hardware/Software co-verification platform for EOS design. The hardware platform contains a microprocessor board and an FPGA (Field Programmable Gate Array)-based verification board, and the corresponding software includes test benches running in FPGAs, controlling programs for the microprocessor and a console program with GUI (Graphical User Interface) interface for configuration, management and supervision. The design is cost-effective and has been successfully employed to verify several IP (Intellectual Property) blocks of our EOS chip. Moreover, it is flexible and can be applied as a general-purpose verification platform.
