This paper analyzes the operation parameters of the time delay and integration (TDI) line scan CCD camera, such as resolution, line rate, clock frequency, etc. and their mathematical relationship is deduced. By analyz...This paper analyzes the operation parameters of the time delay and integration (TDI) line scan CCD camera, such as resolution, line rate, clock frequency, etc. and their mathematical relationship is deduced. By analyzing and calculating these parameters, the working clocks of the TDI CCD line scan camera are designed, which guarantees the synchronization of the line scan rate and the camera movement speed. The IL-E2 TDI CCD of DALSA Co. is used as the sensor of the camera in the paper. The working clock generator used for the TDI CCD sensor is realized by using the programmable logic device (PLD). The experimental results show that the working clock generator circuit satisfies the requirement of high speed TDI CCD line scan camera.展开更多
The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip....The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.展开更多
The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS...The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.展开更多
基金Sponsored by the Research Fund of Harbin Institute of Technology (Grant No.HITMD 2001.18).
文摘This paper analyzes the operation parameters of the time delay and integration (TDI) line scan CCD camera, such as resolution, line rate, clock frequency, etc. and their mathematical relationship is deduced. By analyzing and calculating these parameters, the working clocks of the TDI CCD line scan camera are designed, which guarantees the synchronization of the line scan rate and the camera movement speed. The IL-E2 TDI CCD of DALSA Co. is used as the sensor of the camera in the paper. The working clock generator used for the TDI CCD sensor is realized by using the programmable logic device (PLD). The experimental results show that the working clock generator circuit satisfies the requirement of high speed TDI CCD line scan camera.
基金National High Technology Research and Development Program of China(863 Program)(No.2009AA7010102)
文摘The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.
基金supported by the National Natural Science Foundation of China(Nos.61404090,61434004)
文摘The impact of the parasitic phenomenon on the performance of the analog accumulator in TDI CMOS image sensor is analyzed and resolved. A 128-stage optimized accumulator based on 0.18-μm one-poly four-metal 3.3 V CMOS technology is designed and simulated. A charge injection effect from the top plate sampling is em- ployed to compensate the un-eliminated parasitics based on the accumulator with a decoupling switch, and then a calibration circuit is designed to restrain the mismatch and Process, Voltage and Temperature （PVT） variations. The post layout simulation indicates that the improved SNR of the accumulator upgrades from 17.835 to 21.067 dB, while an ideal value is 21.072 dB. In addition, the linearity of the accumulator is 99.62%. The simulation results of two extreme cases and Monte Carlo show that the mismatch and PVT variations are restrained by the calibration circuit. Furthermore, it is promising to design a higher stage accumulator based on the proposed structure.
