VME system of the Resistive Plate Chamber (RPC) electronics for the Daya Bay Reactor Neutrino Experiment is described in this paper. A 9U VME RPC trigger module (RTM) is designed to process coincidence signals coming ...VME system of the Resistive Plate Chamber (RPC) electronics for the Daya Bay Reactor Neutrino Experiment is described in this paper. A 9U VME RPC trigger module (RTM) is designed to process coincidence signals coming from front end cards (FECs), to generate local triggers and send them to FECs to select the hit data from RPC detector, to report trigger information to a master trigger system and receive cross triggers from the master trigger system. Another 9U VME readout module is designed to collect data from all FECs, to send out configurations to FECs, and to transmit collected hit data to the data acquisition system via VME bus. Test results prove that the VME system is capable of treating a maximum data rate (2.2 MB·s-1 ), without data loss.展开更多
In this paper,a digitalizing board for readout of PMT signals in the prototype array of WCDA(water Cerenkov detector array)for LHAASO(Large high altitude air shower observatory)is designed.The prototype array is compo...In this paper,a digitalizing board for readout of PMT signals in the prototype array of WCDA(water Cerenkov detector array)for LHAASO(Large high altitude air shower observatory)is designed.The prototype array is composed of 9 PMTs,including the pulse time and charge measurement from the PMTs,and clock generation and trigger decision.In the digitalizing board,FPGA reconfiguration and data readout via VME bus are implemented.Test results show that the performances meet well with the requirements of readout electronics.It has been installed in Yangbajing and tests with the prototype array and DAQ is ongoing.展开更多
The time resolution of a radiography system for high-Z materials shall be at least 1 ns, hence the need of a time measurement system with a resolution of about 100 ps. In this paper, a Time Measurement Evaluation Boar...The time resolution of a radiography system for high-Z materials shall be at least 1 ns, hence the need of a time measurement system with a resolution of about 100 ps. In this paper, a Time Measurement Evaluation Board (TMEB) is developed to meet the need. It is based on the time-to-digital converter of ACAM TDC-GP2. Test results show an overall time resolution of 81 ps in detecting cosmic-rays with a plastic scintillator.展开更多
This fully digital beam position measurement instrument is designed for beam position monitoring and machine research in Shanghai Synchrotron Radiation Facility. The signals received from four position-sensitive detec...This fully digital beam position measurement instrument is designed for beam position monitoring and machine research in Shanghai Synchrotron Radiation Facility. The signals received from four position-sensitive detectors are narrow pulses with a repetition rate up to 499.654 MHz and a pulse width of around 100 ps, and their dynamic range could vary over more than 40 dB in machine research. By the employment of the under-sampling technique based on high-speed high-resolution A/D conversion, all the processing procedure is performed fully by the digital signal processing algorithms integrated in one single Field Programmable Gate Array. This system functions well in the laboratory and commissioning tests, demonstrating a position resolution (at the turn by turn rate of 694 kHz) better than 7 μm over the input amplitude range of -40 dBm to 10 dBm which is well beyond the requirement.展开更多
A high resolution time measurement system with high data transfer rate was designed for the COLTRIMS (Cold Target Recoil-Ion Momentum Spectroscopy) system in Institute of Modern Physics,Chinese Academy of Sciences.It ...A high resolution time measurement system with high data transfer rate was designed for the COLTRIMS (Cold Target Recoil-Ion Momentum Spectroscopy) system in Institute of Modern Physics,Chinese Academy of Sciences.It is used to measure the Time of Flight(TOF) with a high resolution for all 20 channels.Based on the PCI Extensions for Instrumentation(PXI) standard,the readout electronics system consists of one Clock-Trigger fan-out module and four TOF modules.Test results show that the system meets the demands of COLTRIMS,with a time resolution of better than 25 ps and a data transfer rate over 20 MB/s.展开更多
The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed ...The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.展开更多
The architecture of carry chains in Field-Programmable Gate Array(FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the archi...The architecture of carry chains in Field-Programmable Gate Array(FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8 N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter(TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy.展开更多
Some specified chips in traditional Manchester-Ⅱencoding/decoding designs are used to guarantee strictly the stability of the input wave,otherwise the capacity of anti-interference and resilience are degraded serious...Some specified chips in traditional Manchester-Ⅱencoding/decoding designs are used to guarantee strictly the stability of the input wave,otherwise the capacity of anti-interference and resilience are degraded seriously.In this paper,a new Manchester-Ⅱencoding/ decoding system is used for nuclear logging by a 7 000 m armoring cable.A thorough hardware wave tracking decoding algorithm is proposed and realized in a FPGA hardware chip.An on-site measurements show that this transmission system can decode correctly in real time,with a bit error rate of better than 10^(-10).展开更多
For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchron...For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.展开更多
In this paper,we report a clock distribution system for Water Cherenkov Detector Arrays(WCDAs) in Large High Altitude Air Shower Observatory(LHAASO) project.The designed electronics system is of high performance in im...In this paper,we report a clock distribution system for Water Cherenkov Detector Arrays(WCDAs) in Large High Altitude Air Shower Observatory(LHAASO) project.The designed electronics system is of high performance in implementing the clock distribution among detectors of a large scale of dimension.Based on Serializer/Deserializer(SerDes) and fiber transmission,the clock distribution system is the modules of central back end to distributed front end.The clock distribution system has been evaluated with a two modules system.While all the four SerDes candidates for clock transmission with jitters below 17 ps,the DS92LV16 has a fixed phase relationship between transmission clock and recovered clock,hence its use in LHAASO WCDAs.展开更多
Compared with traditional waveform digitization with flash-ADCs, waveform digitization with switched-capacitor arrays (SCAs) is able to achieve the sampling speed above 1 GS/s without degrading the analog to digital c...Compared with traditional waveform digitization with flash-ADCs, waveform digitization with switched-capacitor arrays (SCAs) is able to achieve the sampling speed above 1 GS/s without degrading the analog to digital conversion precision significantly. In this paper, we present the implementation of a fast waveform digitization system with the use of SCAs, and evaluate its performance of waveform digitization and the waveform timing. At about 5 GS/s, the dynamic input range of the digitizer is about 66 dB, and its timing precision is about 20 ps (RMS).展开更多
Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch erro...Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.展开更多
The prototype of a time digitizing system for the BESⅢ endcap TOF （ETOF） upgrade is introduced in this paper, The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive pl...The prototype of a time digitizing system for the BESⅢ endcap TOF （ETOF） upgrade is introduced in this paper, The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber （MRPC） are signaled as LVDS by front-end electronics （FEE） and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module （TDIG） of this prototype can support up to 72 electrical channels for hit information measurement. The fast control （FCTL） module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF （BTOF） structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.展开更多
Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with t...Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer（PHY） is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission.This kind of data path is fully implemented by hardware. From the side of the data acquisition system（DAQ）,however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented.Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner.展开更多
An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （E...An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.展开更多
Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measuremen...Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays（FPGAs）, FPGA time-to-digital converters（TDCs） have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold（TOT） measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC＇s integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.展开更多
With increasing physical event rates and the number of electronic channels, traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane. In this pap...With increasing physical event rates and the number of electronic channels, traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane. In this paper, a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ. Features of explicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments. Furthermore,to guarantee the readout performance and flexibility, a standalone embedded CPU system is utilized for network protocol stack processing. To receive the customized data format and protocol from front-end electronics, a field programmable gate array（FPGA） is used for logic reconfiguration. To optimize the interface and to improve the data throughput between CPU and FPGA, a sophisticated method based on SRAM is presented in this paper. For the purpose of evaluating this high-speed readout method, a simplified readout module is designed and implemented.Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.展开更多
基金Supported by National Natural Science Foundation of China (Grant No.10890091)Guangdong Province and Chinese Academy of Sciences’Comprehensive Strategic Cooperation Projects (No.2011A090100015)
文摘VME system of the Resistive Plate Chamber (RPC) electronics for the Daya Bay Reactor Neutrino Experiment is described in this paper. A 9U VME RPC trigger module (RTM) is designed to process coincidence signals coming from front end cards (FECs), to generate local triggers and send them to FECs to select the hit data from RPC detector, to report trigger information to a master trigger system and receive cross triggers from the master trigger system. Another 9U VME readout module is designed to collect data from all FECs, to send out configurations to FECs, and to transmit collected hit data to the data acquisition system via VME bus. Test results prove that the VME system is capable of treating a maximum data rate (2.2 MB·s-1 ), without data loss.
基金Supported by Knowledge Innovation Program of the Chinese Academy of Sciences(Grant No.KJCX2-YW-N31)
文摘In this paper,a digitalizing board for readout of PMT signals in the prototype array of WCDA(water Cerenkov detector array)for LHAASO(Large high altitude air shower observatory)is designed.The prototype array is composed of 9 PMTs,including the pulse time and charge measurement from the PMTs,and clock generation and trigger decision.In the digitalizing board,FPGA reconfiguration and data readout via VME bus are implemented.Test results show that the performances meet well with the requirements of readout electronics.It has been installed in Yangbajing and tests with the prototype array and DAQ is ongoing.
基金Supported by National Natural Science Foundation of China(Grant No.11005108)
文摘The time resolution of a radiography system for high-Z materials shall be at least 1 ns, hence the need of a time measurement system with a resolution of about 100 ps. In this paper, a Time Measurement Evaluation Board (TMEB) is developed to meet the need. It is based on the time-to-digital converter of ACAM TDC-GP2. Test results show an overall time resolution of 81 ps in detecting cosmic-rays with a plastic scintillator.
基金Supported by Knowledge Innovation Program of The Chinese Academy of Sciences (KJCX2-YW-N27)the National Natural Science Foundation of China (10875119)100 Talents Program of The Chinese Academy of Sciences
文摘This fully digital beam position measurement instrument is designed for beam position monitoring and machine research in Shanghai Synchrotron Radiation Facility. The signals received from four position-sensitive detectors are narrow pulses with a repetition rate up to 499.654 MHz and a pulse width of around 100 ps, and their dynamic range could vary over more than 40 dB in machine research. By the employment of the under-sampling technique based on high-speed high-resolution A/D conversion, all the processing procedure is performed fully by the digital signal processing algorithms integrated in one single Field Programmable Gate Array. This system functions well in the laboratory and commissioning tests, demonstrating a position resolution (at the turn by turn rate of 694 kHz) better than 7 μm over the input amplitude range of -40 dBm to 10 dBm which is well beyond the requirement.
基金Supported by the Knowledge Innovation Program of Chinese Academy of Sciences under Grant No.KJCX2-YW-N27
文摘A high resolution time measurement system with high data transfer rate was designed for the COLTRIMS (Cold Target Recoil-Ion Momentum Spectroscopy) system in Institute of Modern Physics,Chinese Academy of Sciences.It is used to measure the Time of Flight(TOF) with a high resolution for all 20 channels.Based on the PCI Extensions for Instrumentation(PXI) standard,the readout electronics system consists of one Clock-Trigger fan-out module and four TOF modules.Test results show that the system meets the demands of COLTRIMS,with a time resolution of better than 25 ps and a data transfer rate over 20 MB/s.
基金Supported by BEPCII project (BEPC II-UDDETF-309-HT182/2004)Knowledge Innovation Program of The Chinese Academy of Sciences (YFKJCX3. SYW. N5)the National Natural Science Foundation of China (No.10970033)
文摘The impact of the integral non-linearity (INL) to the time resolution of HPTDC (High Performance Time to Digital Converter) is presented in this paper.An INL correction method based on look-up table (LUT),is proposed to minimize such INL and improve the time resolution.This scheme is implemented in a single Field Programmable Gate Array (FPGA) device for real-time compensation.The INL characteristic estimation is based on a statistical approach,in which a sufficiently large number of random input signals are measured.The prototype tests show that the deviation for time resolution due to INL can be reduced greatly,from more than 80 ps to less than 20 ps,which can meet the requirement of BES (Beijing Spectrometer) III Time-Of-Flight detector.
文摘The architecture of carry chains in Field-Programmable Gate Array(FPGA) is introduced in this paper. The propagation delay time of the rising and falling edges in the carry chains are calculated according to the architecture and they are predicted not equal in most cases. Tests show that the measuring results of the propagation delay time in EP3C120F484C8 N series FPGA of Altera are in line with the inference. The difference of propagation delay time results in different accuracies of Time-to-Digital Converter(TDC). This phenomenon shall be considered in the design of TDC implemented in FPGA. It can ensure better accuracy.
基金Supported by the China National High Technology Research and Development Program(863 Plans) funding for this project(No,2006AA09A102-02)
文摘Some specified chips in traditional Manchester-Ⅱencoding/decoding designs are used to guarantee strictly the stability of the input wave,otherwise the capacity of anti-interference and resilience are degraded seriously.In this paper,a new Manchester-Ⅱencoding/ decoding system is used for nuclear logging by a 7 000 m armoring cable.A thorough hardware wave tracking decoding algorithm is proposed and realized in a FPGA hardware chip.An on-site measurements show that this transmission system can decode correctly in real time,with a bit error rate of better than 10^(-10).
基金Supported by the National Natural Science Foundation of China(No.11005107)Anhui University Natural Science Research(No.K J2010A334)
文摘For modern particle physics experiments,trigger-less data acquisition(DAQ) system has been put into practice because of the need of reaction multiplicity and trigger flexibility.In such new DAQ systems,global synchronized clock plays an important role because it affects the granularity of time slice and precision of reference clock.In this paper,a novel synchronized clock distribution method is proposed.With the help of modulation technique,master clock module distributes system clock to each slave module.To synchronize slave clocks,the propagation delay is adjusted and the clock phase is aligned by an FPGA chip automatically.Furthermore,an ADCbased method is proposed to evaluate the performance of multi-module clock synchronization simultaneously.The experiments of a prototype system show that slave clocks can be synchronized less than 100 ps over 150 m range.The proposed method is simple and flexible,and it can be used in trigger-less DAQ system and other applications of clock distribution preciously.
基金Supported by the Knowledge Innovation Program of Chinese Academy of Sciences(Grant No.KJCX2-YW-N31)
文摘In this paper,we report a clock distribution system for Water Cherenkov Detector Arrays(WCDAs) in Large High Altitude Air Shower Observatory(LHAASO) project.The designed electronics system is of high performance in implementing the clock distribution among detectors of a large scale of dimension.Based on Serializer/Deserializer(SerDes) and fiber transmission,the clock distribution system is the modules of central back end to distributed front end.The clock distribution system has been evaluated with a two modules system.While all the four SerDes candidates for clock transmission with jitters below 17 ps,the DS92LV16 has a fixed phase relationship between transmission clock and recovered clock,hence its use in LHAASO WCDAs.
基金Supported by the Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27)the National Natural Science Foundation of China (No. 11175176)
文摘Compared with traditional waveform digitization with flash-ADCs, waveform digitization with switched-capacitor arrays (SCAs) is able to achieve the sampling speed above 1 GS/s without degrading the analog to digital conversion precision significantly. In this paper, we present the implementation of a fast waveform digitization system with the use of SCAs, and evaluate its performance of waveform digitization and the waveform timing. At about 5 GS/s, the dynamic input range of the digitizer is about 66 dB, and its timing precision is about 20 ps (RMS).
基金Supported by Knowledge Innovation Program of Chinese Academy of Sciences(KJCX2-YW-N27)National Natural Science Foundation of China(11175176,10476028)
文摘Time interleaved analog-to-digital conversion （TIADC） based on parallelism is an effective way to meet the requirement of the ultra-fast waveform digitizer beyond Gsps. Different methods to correct the mismatch errors among different analog-to-digital conversion channels have been developed previously. To overcome the speed limi- tation in hardware design and to implement the mismatch correction algorithm in real time, this paper proposes a fully parallel correction algorithm. A 12-bit l-Gsps waveform digitizer with ENOB around 10.5 bit from 5 MHz to 200 MHz is implemented based on the real-time correction algorithm.
基金Supported by National Natural Science Foundation of China(10979003,11005107)
文摘The prototype of a time digitizing system for the BESⅢ endcap TOF （ETOF） upgrade is introduced in this paper, The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber （MRPC） are signaled as LVDS by front-end electronics （FEE） and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module （TDIG） of this prototype can support up to 72 electrical channels for hit information measurement. The fast control （FCTL） module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF （BTOF） structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps.
基金Supported by National Natural Science Foundation of China(11005107)Independent Projects of State Key Laboratory of Particle Detection and Electronics(201301)
文摘Due to its advantages of universality, flexibility and high performance, fast Ethernet is widely used in readout system design for modern particle physics experiments. However, Ethernet is usually used together with the TCP/IP protocol stack, which makes it difficult to implement readout systems because designers have to use the operating system to process this protocol. Furthermore, TCP/IP degrades the transmission efficiency and real-time performance. To maximize the performance of Ethernet in physics experiment applications, a data readout method based on the physical layer（PHY） is proposed. In this method, TCP/IP is replaced with a customized and simple protocol, which makes it easier to implement. On each readout module, data from the front-end electronics is first fed into an FPGA for protocol processing and then sent out to a PHY chip controlled by this FPGA for transmission.This kind of data path is fully implemented by hardware. From the side of the data acquisition system（DAQ）,however, the absence of a standard protocol causes problems for the network related applications. To solve this problem, in the operating system kernel space, data received by the network interface card is redirected from the traditional flow to a specified memory space by a customized program. This memory space can easily be accessed by applications in user space. For the purpose of verification, a prototype system has been designed and implemented.Preliminary test results show that this method can meet the requirements of data transmission from the readout module to the DAQ with an efficient and simple manner.
基金Supported by National Natural Science Foundation of China(10979003,11005107)CAS Center for Excellence in Particle Physics(CCEPP)
文摘An automatic clock synchronization method implemented in a field programmable gate array （FPGA） is proposed in this paper. It is developed for the clock system which will be applied in the end-cap time of flight （ETOF） upgrade of the Beijing Spectrometer （BESIII）. In this design, an FPGA is used to automatically monitor the synchronization circuit and deal with signals coming from the external clock synchronization circuit. By testing different delay time of the detection signal and analyzing the signal state returned~ the synchronization windows can be found automatically by the FPGA. The new clock system not only retains low clock jitter which is less than 20ps root mean square （RMS）, but also demonstrates automatic synchronization to the beam bunches. So far, the clock auto-synchronizing function has been working successfully under a series of tests. It will greatly simplify the system initialization and maintenance in the future.
基金Supported by National Natural Science Foundation of China(11079003,10979003)
文摘Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays（FPGAs）, FPGA time-to-digital converters（TDCs） have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold（TOT） measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC＇s integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.
基金Supported by National Natural Science Foundation of China(11005107)Independent Projects of State Key Laboratory of Particle Detection and Electronics(201301)
文摘With increasing physical event rates and the number of electronic channels, traditional readout schemes meet the challenge of improving readout speed caused by the limited bandwidth of the crate backplane. In this paper, a high-speed data readout method based on the Ethernet is presented to make each readout module capable of transmitting data to the DAQ. Features of explicitly parallel data transmitting and distributed network architecture give the readout system the advantage of adapting varying requirements of particle physics experiments. Furthermore,to guarantee the readout performance and flexibility, a standalone embedded CPU system is utilized for network protocol stack processing. To receive the customized data format and protocol from front-end electronics, a field programmable gate array（FPGA） is used for logic reconfiguration. To optimize the interface and to improve the data throughput between CPU and FPGA, a sophisticated method based on SRAM is presented in this paper. For the purpose of evaluating this high-speed readout method, a simplified readout module is designed and implemented.Test results show that this module can support up to 70 Mbps data throughput from the readout module to DAQ.
